Integrated Cluster Bus performance for the IBM S/390 Parallel Sysplex

Abstract

IntegratedCluster Bus performance for the IBM S/390 Parallel Sysplex As the speed of the S/390 ® processors has increased at a rapid rate over the years, it has become extremely challenging to be able to connect them in a Parallel Sysplex ® without compromising system performance. The cost of synchronous accesses to the coupling facility will build up progressively unless coupling link technology keeps pace with the development of the processors. Beginning with the G5 processors, IBM has introduced the ICB coupling link technology to enhance the performance of closely integrated processor clusters. With a high data transmission rate complemented by reduced hardware and microcode path lengths, the ICB provides excellent coupling efficiency. This paper emphasizes the need for the ICB and discusses the superior performance delivered by this latest coupling link technology.

Coupling I/O channels for the IBM eServer z900: Reengineering required

“…With the 8B/10B transmission code, the bandwidth increased to more than 200 MB/s. The resulting coupling efficiency remained close to 80% [7,8].…”

Functional verification of a frequency-programmable switch chip with asynchronous clock sections

“…The STI switch chip provides high-speed connections between the memory bus adapter (MBA) and the I/O attachments [2] and to other systems within the Parallel Sysplex* [3]. The switch chip is also called the multiplexor/ demultiplexor chip.…”