Instruction set extensions for Dynamic Time Warping

Abstract

Processor specialization through application-specific instruction set customization can significantly improve performance while reducing energy. Due to the costs associated with semiconductor fabrication, specialized processors are only viable for products with high production volumes. The emergence of low-cost sensorbased computing products in recent years has created an urgent need to process time-series data with the utmost efficiency. Although most sensor data is fixed-point, the normalization process-an absolute necessity for highly accurate similarity search of time-series data-converts the data to floating-point in order to avoid a loss in precision. The sensors that collect timeseries data are typically connected to low-power microcontrollers or RISC processors sans floating point units. The computational requirements of real-time similarity search would overwhelm such processors. To address this concern, we introduce a specialized instruction set for time-series data mining applications to a 32-bit embedded processor, yielding a 4.87x performance improvement and a 78% reduction in energy consumption compared to a highly optimized software implementation.

Accelerating the dynamic time warping distance measure using logarithmetic arithmetic

“…Table II lists the instruction and data cache configurations that we used, which is the same as Ref. [7]. We enabled 64-bit fixed-point multiplication, a hardware divider, and a branch target cache with 2048 entries.…”

“…[7]: ISE-Norm, ISE-DTW, ISE-Accum, and ISE-SD. In the discussion that follows the two time series whose similarity is being measured are the query Q and the candidate C; q i and c i are the i th respective data points of the query and candidate.…”

“…Such an SoC could benefit from application-specific customization for time series similarity search, due to its overall ubiquity; however, full-blown ASIC accelerators would likely be too large and too costly. A cheaper solution is to customize the microcontroller at the core of the SoC with a small set of application-specific instruction set extensions (ISEs) that offer much of the desired performance and/power energy benefits that one would obtain from an ASIC, but at a fraction of the cost [7]. This paper explores the use of logarithmic arithmetic, rather than floating-point, in a set of four ISEs that have already been shown to be beneficial for DTW.…”

“…In Ref. [7], the ISEs were implemented using compound floating-point operators that were optimized for an FPGA implementation by the FloPoCo arithmetic compiler [2]. This work replaces the floating-point operations within each ISE with operations based on logarithmetic arithmetic; the result is further improvements in performance and energy consumption by identical factors of 1.8x.…”

“…In the embedded domain, Ref. [7] ported the software to an embedded processor and introduced four floating-point ISEs for acceleration; the system was prototyped and evaluated using an FPGA. At the highest compiler optimization level (gcc -O3), the floating-point ISEs improved performance by a factor of 1.4x and energy consumption by a factor of 2.9x compared a baseline variant of the processor which included a floating-point ALU.…”