Instruction set extension with shadow registers for configurable processors

Cong, Jason; Fan, Yiping; Han, Guoling; Jagannathan, Ashok; Reinman, Glenn; Zhang, Zhiru

doi:10.1145/1046192.1046206

Cited by 49 publications

(28 citation statements)

References 24 publications

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“…Binding of base-processor registers to custom state registers at compile time reduces the amount of data transfers. Use of shadow registers [35] and exploitation of forwarding paths of the base processor [36] can improve the data bandwidth.…”

Section: Background and Related Workmentioning

confidence: 99%

CHIPS: Custom Hardware Instruction Processor Synthesis

Atasu

Özturan

Dündar

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper describes an integer-linear-programming (ILP)-based system called Custom Hardware Instruction Processor Synthesis (CHIPS) that identifies custom instructions for critical code segments, given the available data bandwidth and transfer latencies between custom logic and a baseline processor with architecturally visible state registers. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions. We describe a design flow to identify promising area, performance, and code-size tradeoffs. We study the effect of input/output constraints, register-file ports, and compiler transformations such as if-conversion. Our experiments show that, in most cases, the solutions with the highest performance are identified when the input/output constraints are removed. However, input/output constraints help our algorithms identify frequently used code segments, reducing the overall area overhead. Results for 11 benchmarks covering cryptography and multimedia are shown, with speed-ups between 1.7 and 6.6 times, code-size reductions between 6% and 72%, and area costs ranging between 12 and 256 adders for maximum speed-up. Our ILP-based approach scales well: benchmarks with basic blocks consisting of more than 1000 instructions can be optimally solved, most of the time within a few seconds.Index Terms-Application-specific instruction-set processors (ASIPs), custom instructions, customizable processors, extensible processors, integer linear programming (ILP), optimization algorithms.

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Section: Background and Related Workmentioning

confidence: 99%

CHIPS: Custom Hardware Instruction Processor Synthesis

Atasu

Özturan

Dündar

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Shadow registers duplicate a subset of base processor registers [9] to increase the data bandwidth. The mapping between base processor registers and shadow registers can be fixed, or established at compile time.…”

Section: Related Workmentioning

confidence: 99%

“…The approaches described in [13] and [9] are complementary to ours, since our formulation can take advantage of the increased data bandwidth. The approach of Pozzi et al [14] can be combined with ours to further optimize the performance of multi-cycle instruction-set extensions.…”

Section: Related Workmentioning

confidence: 99%

Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints

Atasu

Dimond

Mencer

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…Though the previous works [4,5,12] improve the data bandwidth, they do not address the related problems of encoding multiple operands in a fixed-length instruction format and data hazards.…”

Section: Related Workmentioning

confidence: 99%

Exploiting forwarding to improve data bandwidth of instruction-set extensions

Jayaseelan¹,

Liu²,

Mitra³

2006

2006 43rd ACM/IEEE Design Automation Conference

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Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performance benefit require multiple input operands. Unfortunately, RISC-style embedded processors are designed to support at most two input operands per instruction. This data bandwidth problem is due to the limited number of read ports in the register file per instruction as well as the fixed-length instruction encoding. We propose to overcome this restriction by exploiting the data forwarding feature present in processor pipelines. With minimal modifications to the pipeline and the instruction encoding along with cooperation from the compiler, we can supply up to two additional input operands per custom instruction. Experimental results indicate that our approach achieves 87-100% of the ideal performance limit for standard benchmark programs. Additionally, our scheme saves 25% energy on an average by avoiding unnecessary accesses to the register file.

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Instruction set extension with shadow registers for configurable processors

Cited by 49 publications

References 24 publications

CHIPS: Custom Hardware Instruction Processor Synthesis

CHIPS: Custom Hardware Instruction Processor Synthesis

Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints

Exploiting forwarding to improve data bandwidth of instruction-set extensions

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