Instruction scheduling for a tiled dataflow architecture

Abstract

This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effectively minimizes operand latency. After this schedule has been partitioned into large sections, the bottom-level algorithm must more carefully analyze program structure when producing the final schedule.Our analysis reveals that at this bottom level, good scheduling depends upon carefully balancing instruction contention for processing elements and operand latency between producer and consumer instructions. We develop a parameterizable instruction scheduler that more effectively optimizes this trade-off. We use this scheduler to determine the contention-latency sweet spot that generates the best instruction schedule for each application. To avoid this application-specific tuning, we also determine the parameters that produce the best performance across all applications. The result is a contention-latency setting that generates instruction schedules for all applications in our workload that come within 17% of the best schedule for each.

Loop-Aware Instruction Scheduling with Dynamic Contention Tracking for Tiled Dataflow Architectures

“…Loading instructions onto the grid is done through co-operation of the microarchitecture and the runtime system. When an instruction produces a result for a consumer instruction not already on the grid, the runtime system is signalled [6]. The placement of the incoming instruction is decided using either a statically constructed table, or an online algorithm which creates a new mapping.…”

“…Inter-cluster communication is through a dynamically-routed packet network. Recently, a hierarchical instruction scheduling algorithm [6] has been proposed for the WaveScalar architecture, which partitions the application's dataflow graph into smaller groups, and assign these groups to PEs. We augmented hierarchical instruction scheduling algorithm to take into consideration the control flow information (i.e.…”

A Scheduling Framework for Spatial Architectures Across Multiple Constraint-Solving Theories

“…Instead, the focus of architecture-specific schedulers has typically been on developing polynomial-time algorithms that approximate the optimal solution using knowledge about the architecture. Chronologically, this body of work includes the BUG scheduler for VLIW proposed in 1985[Ellis 1985, UAS scheduler for clustered VLIW [Özer et al 1998], synchronous dataflow graph scheduling [Battacharyya et al 1996], RAW scheduler [Lee et al 1998], CARS VLIW code generation and scheduler [Kailas et al 2001], TRIPS scheduler [Coons et al 2006;Nagarajan et al 2004], Wavescalar scheduler [Mercaldi et al 2006a], and CCA scheduler proposed in 2008 . While heuristic-based approaches are popular and effective, they have three problems: (1) poor compiler developer/architect productivity since new algorithms, heuristics, and implementations are required for each architecture; (2) lack of insight on optimality of solution; and (3) sandboxing of heuristics to specific architectures-understanding and using techniques developed for one spatial architecture in another is very hard.…”

A general constraint-centric scheduling framework for spatial architectures

“…Instead, the focus of architecture-specific schedulers has typically been on developing polynomial-time algorithms that approximate the optimal solution using knowledge about the architecture. Chronologically, this body of work includes the BUG scheduler for VLIW proposed in 1985 [17], UAS scheduler for clustered VLIW [41], synchronous data-flow graph scheduling [7], RAW scheduler [36], CARS VLIW code-generation and scheduler [33], TRIPS scheduler [12,40], Wavescalar scheduler [37], and CCA scheduler proposed in 2008 [43]. While heuristic-based approaches are popular and effective, they have three problems: i) poor compiler developer/architect productivity since new algorithms, heuristics, and implementations are required for each architecture, ii) lack of insight on optimality of solution, and iii) sandboxing of heuristics to specific architectures -understanding and using techniques developed for one spatial architecture in another is very hard.…”