Instruction merging to increase parallelism in VLIW architectures

Payá-Vayá, Guillermo; Martin-Langerwerf, J.; Giesemann, Florian; Blume, Holger; Pirsch, P.

doi:10.1109/socc.2009.5335660

Cited by 8 publications

(3 citation statements)

References 6 publications

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“…The generic FPGA infrastructure template comprises an OCP multilayer bus, the ethernet DMA interface, SDRAM controllers, on-chip memories and massively parallel parameterized softcore processors [20]. It has been adapted to and tested on a Xilinx Virtex-6 LX550T based BEE4 rapid prototyping system, the Xilinx Virtex-6 ML605 Evaluation Kit and the Virtex-5 LX220 based MCPA board [2] developed at IMS, see Fig.…”

Section: Development Frameworkmentioning

confidence: 99%

Interference Alignment for UWB-MIMO Communication Systems

El–Hadidy¹,

El-Absi²,

Sit³

et al. 2013

Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

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Section: Development Frameworkmentioning

confidence: 99%

Interference Alignment for UWB-MIMO Communication Systems

El–Hadidy¹,

El-Absi²,

Sit³

et al. 2013

Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

Self Cite

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“…Other features, like a X4 conditional execu tion mechanism or an extended X4 operation mode, can also be adapted from those described in [6].…”

Section: Vliw Architecture Optimizationsmentioning

confidence: 99%

“…More narrowly, it proposes a new mechanism, called X4 operation mode, that allows to concurrently use more functional units (FU) or special FUs with wider input/output operands without increasing the number of instructions to decode or the silicon area required by the register file. This mechanism is an extension of a previously published instruc tion merging technique [6]. Moreover, a complex FU, which employs the X4 operation mode, has also been developed for processing a typical stereoscopic application under real-time conditions.…”

mentioning

confidence: 99%

VLIW architecture optimization for an efficient computation of stereoscopic video applications

Payá-Vayá

Martin-Langerwerf

Banz

et al. 2010

The 2010 International Conference on Green Circuits and Systems

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This paper presents two new architecture optimiza tions to improve the processing performance of video applications with a high degree of data parallelism in VLIW processors. On the one hand, a new register file access mechanism, called X4 operation mode, allows to access wide operands made up of several consecutive registers in the register file, while keeping its normal functionality (i.e. single read/write register access). On the other hand, a new functional unit is proposed to efficiently process a typical stereoscopic video application based on a rank transformation and a semi-global-matching algorithm. An evaluation of those enhanced mechanisms is performed using a generic VLIW architecture and the resulting VLIW processor is compared with other CPU/GPU and FPGA implementations. The proposed architecture provides the full flexibility of a programmable processor, while processing 64Ox480 stereo video sequences under real-time conditions, what is not possible with the compared CPUs or GPUs. I. INT RODUCTIONStereo matching is one of the most researched topics in com puter vision and is used to extract detailed depth information (disparity information) from passive stereo-camera systems. This is required in numerous machine vision applications like driver assistance systems or 3D video processing. On the one hand, systems based on passive stereo-cameras can provide highly accurate three dimensional details with a lower cost than those based on active radar or lidar sensors. Moreover, the same camera system can be used to perform other kinds of video processing, such as pedestrian, vehicle, or road detection. On the other hand, the algorithms used to extract the depth information from those video stereo-camera systems require a high computational load and the use of dedicated hardware embedded systems to provide real-time processing capabilities. Several autonomous embedded system solutions based on dedicated hardware structures, specially designed for an FPGA or ASIC technology, can be found in literatureThe use of a programmable embedded processor in com puter vision systems allows to easily introduce new algorithm modifications by just modifying the application code without requiring to redesign the complete hardware architecture. At the Institute of Microelectronic Systems, the research project RAPANUI [4] provides a complete design space exploration environment based on a generic VLIW architecture, which includes a parameterized pipeline architecture simulator, an aggressive instruction scheduler, and a parameterized HDL description of the generic VLIW architecture [5]. By using this environment, the generic VLIW architecture can be optimized and improved in terms of performance and hardware cost for a specific group of applications. This paper is focused on novel VLIW architecture optimiza tions for efficient processing of stereoscopic video applica tions. More narrowly, it proposes a new mechanism, called X4 operation mode, that allows to concurrently use more functional units (FU) or special FUs with wi...

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