Inspection and metrology challenges for 3 nm node devices and beyond

Unavoidable renaissance of electron metrology in the age of high numerical aperture extreme ultraviolet lithography

“…Being able to characterize 3D structures is a critical requirement in a world where device architecture is becoming more and more complex and vertical. In the following, we report on the creative use of high voltage e-beam metrology measurements, to characterize lateral recess in gate-all-around (GAA) SiGe devices 9 …”

“…In the following, we report on the creative use of high voltage e-beam metrology measurements, to characterize lateral recess in gate-all-around (GAA) SiGe devices. 9 The usual approach to cavity recess metrology, utilizing TEM on a limited number of locations, is disruptive and statistically not representative of the full wafer. By contrast, extracting 3D information from these features using standard e-beam metrology in the typical energy ranges proves to be unfeasible.…”

Interface Investigation on SiGe/Si Multilayer Structures: Influence of Different Epitaxial Process Conditions

“…10 The SiGe/Si stacked quantum well or superlattice structure can also be widely used in optoelectronic devices, 11 and the sharpness of the internal interface will be reflected in the absorption and reflection performance of electron and photon. 1,2,12 The group IV material epitaxy processes mainly consist of molecular-beam epitaxy (MBE) and chemical vapor deposition (CVD). CVD has been widely adopted by the industry for its higher growth efficiency and 8−12 in.…”

“…For gate-all-around (GAA) field-effect transistors (FETs) beyond the 3 nm technology node, alternating Si and SiGe multilayer (MLs) were grown as the first step in the fabrication process. The interface between SiGe and Si layers must be as abrupt/sharp as possible in order to control etching and to further precisely control the final Si nanowire/nanosheet surface roughness and profile. − For electron spin qubits in a compressive strain Si quantum well, a sharp and flat interface can effectively reduce the scattering and noise during charge manipulation. ,− The valley splitting is caused by the sharp potential barrier between the SiGe/Si interface and is very sensitive to the details of interface, such as, strain, mismatch, abruptness, etc . The SiGe/Si stacked quantum well or superlattice structure can also be widely used in optoelectronic devices, and the sharpness of the internal interface will be reflected in the absorption and reflection performance of electron and photon. ,, …”