Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k/metal gate stacks

Batude, P.; Garros, X.; Clavelier, L.; Royer, C. Le; Hartmann, J.-M.; Loup, V.; Besson, P.; Vandroux, L.; Campidelli, Y.; Deleonibus, S.; Boulanger, F.

doi:10.1063/1.2767381

Cited by 47 publications

(28 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This occurs more for MOS-devices with smaller bandgap materials then Si and at higher temperatures. Because of the smaller Ge bandgap, the interface traps in the minority half of the bandgap contribute to the C-V and G-V at room temperature in the 1kHz -1MHz range [9,10]. The weak inversion (WI) response in Ge has similar features in C-V and G-V characteristics as a depletion bias response.…”

Section: The Full Conductance Techniquementioning

confidence: 84%

Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs

Martens

Mitard

Jaeger

et al. 2008

ESSDERC 2008 - 38th European Solid-State Device Research Conference

View full text Add to dashboard Cite

The semiconductor-dielectric interface passivation of Ge pMOSFETs with an epitaxially grown Si-layer is studied by means of the full conductance technique. This technique resolves several issues which occur for alternative MOSinterfaces when using the 'classical' conductance technique. The observed mobility behavior as a function of Si-passivation thickness can be explained by the observed variation in interface state density. Observed threshold voltage shifts as a function of Si-passivation thickness can also be linked to the variation in interface state density with thickness.

show abstract

Section: The Full Conductance Techniquementioning

confidence: 84%

Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs

Martens

Mitard

Jaeger

et al. 2008

ESSDERC 2008 - 38th European Solid-State Device Research Conference

View full text Add to dashboard Cite

show abstract

“…However, the capacitance in this bias range still remains high for the 1 MHz curve, which is not expected for typical minority carrier lifetimes in silicon. 18,19 In the case of a low frequency CV response due to the generation and recombination of minority carriers in the depletion region of the silicon, low frequency CV characteristics are not typically recorded at frequencies above 100 Hz. 18,19 A possible explanation for this effect is shown in Figure 3, which shows plan and cross sectional views of MOS capacitors with different gate areas, where charge exists on the oxide surface, or within the oxide, in the region outside the area defined by the gate electrode.…”

Section: Resultsmentioning

confidence: 99%

Observation of peripheral charge induced low frequency capacitance-voltage behaviour in metal-oxide-semiconductor capacitors on Si and GaAs substrates

O’Connor

Cherkaoui

Monaghan

et al. 2012

Journal of Applied Physics

View full text Add to dashboard Cite

We report on experimental observations of room temperature low frequency capacitance-voltage (CV) behaviour in metal oxide semiconductor (MOS) capacitors incorporating high dielectric constant (high-k) gate oxides, measured at ac signal frequencies (2 kHz to 1 MHz), where a low frequency response is not typically expected for Si or GaAs MOS devices. An analysis of the inversion regions of the CV characteristics as a function of area and ac signal frequency for both n and p doped Si and GaAs substrates indicates that the source of the low frequency CV response is an inversion of the semiconductor/high-k interface in the peripheral regions outside the area defined by the metal gate electrode, which is caused by charge in the high-k oxide and/or residual charge on the high-k oxide surface. This effect is reported for MOS capacitors incorporating either MgO or GdSiOx as the high-k layers on Si and also for Al2O3 layers on GaAs(111B). In the case of NiSi/MgO/Si structures, a low frequency CV response is observed on the p-type devices, but is absent in the n-type devices, consistent with positive charge (>8 × 1010 cm−2) on the MgO oxide surface. In the case of the TiN/GdSiOx/Si structures, the peripheral inversion effect is observed for n-type devices, in this case confirmed by the absence of such effects on the p-type devices. Finally, for the case of Au/Ni/Al2O3/GaAs(111B) structures, a low-frequency CV response is observed for n-type devices only, indicating that negative charge (>3 × 1012 cm−2) on the surface or in the bulk of the oxide is responsible for the peripheral inversion effect.

show abstract

“…Because of the smaller Ge bandgap, the interface traps in the minority half of the bandgap contribute to the C-V and G-V at room temperature in the 1kHz -1MHz range [31][32]. The weak inversion (WI) response in Ge has similar features in C-V and G-V characteristics as a depletion bias response, and can therefore easily be confused.…”

Section: Characterization For Ge and Iii-v Mos Structuresmentioning

confidence: 97%

Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies

Groeseneken

Degraeve

Kaczer

et al. 2010

2010 Proceedings of the European Solid State Device Research Conference

View full text Add to dashboard Cite

In this paper we give a brief historical review of the evolution of device reliability research over the past decades. Then we give some examples on how established characterization techniques that were developed for silicon based devices can be completely misinterpreted when applied to Ge or III-V based MOS-structures, and how a simple modification of the technique can ensure a correct interpretation. We also show how novel techniques, such as TSCIS (Trap spectroscopy by Charge Injection and Sensing). were developed recently to overcome the problem of dielectric material screening for logic and memory applications. With the scaling of the devices into the nanometer regime single traps are causing large variations in the device parameters, which leads to a time-dependent variability, which makes lifetime analysis difficult. Finally we show that when using the classical reliability assessment methodology based on accelerated testing, the available reliability margins are strongly reduced, in some cases even down to zero, especially for sub-1nm EOT (Effective Oxide Thickness) devices. As a result, we argue that the reliability community will have to look for alternative ways to ensure and guarantee the lifetime of future products.

show abstract

Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k/metal gate stacks

Abstract: Articles you may be interested inModeling of n-InAs metal oxide semiconductor capacitors with high-κ gate dielectric

Cited by 47 publications

References 16 publications

Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs

Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs

Observation of peripheral charge induced low frequency capacitance-voltage behaviour in metal-oxide-semiconductor capacitors on Si and GaAs substrates

Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies

Contact Info

Product

Resources

About