Insight into Threshold Voltage and Drain Induced Barrier Lowering in Negative Capacitance Field Effect Transistor

Uddin

Modelling and Simulation in Engineering

et al. 2022

Ferroelectric negative capacitance materials have now been proposed for lowering electronics energy dissipation beyond basic limitations. In this paper, we presented the analysis on the performance of negative capacitance (NC) FinFET in comparison with conventional gate dielectrics by using a separation of variables approach, which is an optimal quasi-3D mathematical model. The result has been signified steeper surface potential (ψ), lower threshold voltage (Vth), 1.2 mA of on-state current (Ion), and enhanced immunity of negative capacitance FinFET against short channel effects (SCE’s) like 35.3 mV/V of drain-induced barrier lowering (DIBL), 60 mV/dec of subthreshold swing (SS) along with smallest off state current (Ioff) among another conventional gate dielectric. Hence, NC FinFET can be a potential candidate for low power and high-performance device.

Section: Resultsmentioning

confidence: 95%

Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET

Uddin

Modelling and Simulation in Engineering

et al. 2022

“…This is due to a mismatch in the ferroelectric capacitance and internal total baseline FinFET capacitances (discussed in 2.1), which should be avoided if such an NCFinFET device is to be used for logic and memory applications [46]. The unique feature: negative DIBL [47] and NDR [48]i nt h e NCFinFET indicating the small model's capacity is shown in Fig. 4(d).…”

Section: Compact Modeling Methodology Of Ncfetmentioning

confidence: 99%

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

Yadav

Kondekar

Awadhiya

et al. 2022

Preprint

Self Cite

In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14nm conventional FinFET to form NC-FinFET. Static and dynamic behaviour of NC-FinFETs is explored and evaluated at different ferroelectric thickness. At supply voltage scaling, important SRAM performance metrics such as stability at different operation condition (hold, read and write mode) and standby leakage power were evaluated. When compared to traditional FinFET-based SRAM, 6T-NCSRAM exhibits distinct behaviour during low and high supply voltages. Moreover, the effect of wordline (WL) voltage pulse variation on 6T-NCSRAM is captured and minimum RC multiplier of 2RC is found to avoid functional failure of 6T-NCSRAM.

“…That is, using the Remanent Polarization, Pr and Coercive Field, Ec in the P-E hysteresis curve, it can be obtained as in Eq. (3) [35]. 52   [34].…”

Section: The Structure Of Ferroelectric Nc Fet and I-v Characteristicsmentioning

confidence: 99%

Analytical Model of Subthreshold Swing for Junctionless Double Gate MOSFET Using Ferroelectric Negative Capacitance Effect

Jung¹

2023

IIUMEJ

An analytical Subthreshold Swing (SS) model is presented to observe the change in the SS when a stacked SiO2-metal-ferroelectric structure is used as the oxide film of a JunctionLess Double Gate (JLDG) MOSFET. The SS of 60 mV/dec or less is essential to reduce power dissipation while maintaining transistor performance. If a ferroelectric material with Negative Capacitance (NC) effect is used, the SS can be reduced below 60 mV/dec. The analytical SS model of the ferroelectric NC FET presented to analyze this was in good agreement with the SS derived from the relation between the drain current and gate voltage, using 2D potential distribution. As results were derived from the analytical SS model, it was found that it is possible to obtain an SS of 60 mV/dec or less even at 15 nm channel length by adjusting the thicknesses of the silicon channel, SiO2, and ferroelectric. In particular, the change in SS according to the ferroelectric thickness was saturated as the thickness of SiO2 increased and was almost constant as the thickness of the silicon channel decreased. ABSTRAK: Model Ayunan Subambang (SS) analitikal dibentangkan bagi melihat perubahan pada SS apabila struktur feroelektrik-logam-SiO2 bertindan digunakan sebagai filem oksida bagi MOSFET Dua Get Tanpa Simpang (JLDG). SS 60 mV/dec atau kurang adalah penting bagi mengurangkan pelesapan kuasa sambil mengekalkan prestasi transistor. Jika bahan feroelektrik dengan kesan Kapasitans Negatif (NC) digunakan, SS dapat dikurangkan bawah 60 mV/dek. Model SS analitikal feroelektrik NC FET yang digunakan bagi kajian ini adalah sesuai dengan SS yang diperoleh daripada hubungan antara arus serapan dan voltan get, menggunakan edaran potensi 2D. Dapatan terbitan melalui model SS analitikal, mendapati bahawa adalah mungkin bagi mendapatkan SS pada 60 mV/dek atau kurang walaupun panjang laluan adalah 15 nm dengan melaraskan ketebalan saluran silikon, SiO2, dan feroelektrik. Terutama apabila perubahan ketebalan feroelektrik SS adalah tepu ketika ketebalan SiO2 meningkat, dan hampir malar apabila ketebalan saluran silikon berkurang.