Conference Record of the 2004 IEEE Industry Applications Conference, 2004. 39th IAS Annual Meeting.
DOI: 10.1109/ias.2004.1348672
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Cited by 22 publications
(17 citation statements)
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“…The layout has a strong effect on these parasitic elements. Thus, keeping parasitic effects low is a major requirement in order to reduce electric power losses, overvoltages and poor current balance during switching phases [2]. Long distances between chips improve the thermal dissipation of power modules, since heat spreads more easily.…”
Section: Introductionmentioning
confidence: 99%
“…The layout has a strong effect on these parasitic elements. Thus, keeping parasitic effects low is a major requirement in order to reduce electric power losses, overvoltages and poor current balance during switching phases [2]. Long distances between chips improve the thermal dissipation of power modules, since heat spreads more easily.…”
Section: Introductionmentioning
confidence: 99%
“…Clearance in inches=0.023"+(0.0002"×V) (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17) where, V is the voltage peak across traces.…”
Section: Example 3 Planar Inductormentioning
confidence: 99%
“…It consists of the low frequency model developed earlier [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] with a lumped high frequency branch connected in parallel. The parameters required for modeling the low frequency model are calculated by nonlinear finite element solutions.…”
Section: Problem Statementmentioning
confidence: 99%
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