IEEE Winter Workshop on Nonlinear Digital Signal Processing

DOI: 10.1109/ndsp.1993.767729

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Input Compression and Efficient Algorithms and Architectures for Stack Filters

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George B. Adams²,

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Cited by 4 publications

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Input compression and efficient VLSI architectures for rank order and stack filters

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et al. 1994

Signal Processing

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Input compression and efficient VLSI architectures for rank order and stack filters

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et al. 1994

Signal Processing

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Fast implementation of non-linear filters using FPGAs

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et al. 1998

IEE Colloquium on Non-Linear Signal and Image Processing

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Most adaptive image and signal processing tasks are performed on specialist digital signal processing chips. These devices are highly optimised for efficient computation of the core multiply and accumulate operations required by current algorithms. Attempts to synthesise these types of algorithms on FPGAs have resulted in few competitive implementations. FPGAs generally fail to realise efficient arithmetic functions except in the most constrained cases such as constant coefficient multipliers 1. The approach adopted in this paper is based on the use of stack filters that avoid these difficulties by employing logical algorithms that do not rely on any arithmetic functions.

A unified approach to implementation of stack filters

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Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers

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