Innovative methods for Burn-In related Stress Metrics Computation

Ruggeri, Walter; Bernardi, Paolo; Littardi, S.; Reorda, M. Sonza; Appello, D.; Bertani, C.; Pollaccia, G.; Tancorre, V.; Ugioli, R.

doi:10.1109/dtis53253.2021.9505067

Cited by 8 publications

(6 citation statements)

References 7 publications

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“…Such a clock is kept stable at the logic value '0' to maintain a static state for a defined amount of time. We named such a measurement as neighborhoodoriented static stress metric [14].…”

Section: Stress Evaluation Metricsmentioning

confidence: 99%

“…In order to select the right kind and amount of patterns needed to reach the same stress coverage by a traditional BI tester, a simulative approach [14] can be used to compute a stress coverage value. Obviously, this simulation step requires the DUT netlist and a proper simulation environment.…”

Section: Pattern Generation Flowmentioning

confidence: 99%

“…In the experimental part of the paper, we show the results obtained on a device for the automotive market, including around 20 million gates, implementing a full scan Design for Testability strategy involving around 700,000 Flip-Flops. The proposed approach reaches 92.18% of toggle activity coverage and 81.0% for the neighborhood-oriented static stress metric [14], described in Section 2.2, by applying 1,024 pseudo-random patterns. This value can be compared with the 90.73% and 76.97% figures, respectively, reached by the purely ATPG-based approach encompassing the application of 32 precomputed patterns.…”

mentioning

confidence: 97%

“…As it is very well known, exhaustive simulation of scan-based stress patterns is very time-consuming (up to months). Therefore, the deductive approach described in [14], is used to parallel load in all scan registers the stress patterns for speeding up the simulation by several orders of magnitude. A parallel engine developed in the frame of the project by the Politecnico di Torino [40] analyzes the simulation VCD file.…”

mentioning

confidence: 99%

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A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

Bernardi

Appello

Bertani

et al. 2023

IEEE Trans. Comput.

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Burn-In test equipment usually owns extensive memory capabilities to store pre-computed patterns to be applied to the circuit inputs as well as ad-hoc circuitries to drive and read the DUT pins during the BI phase. The solution proposed in this paper dramatically reduces the memory size requirement and just demands a generic microcontroller unit (MCU) equipped with a couple of embedded processors, some standard common peripheral units, and a few KB memories. Moreover, the proposed Burn-In tester could be integrated into a System Level Test equipment which is typically based on MCUs to communicate functionally with the DUT. This paper provides full details about the architecture of such a low-cost innovative tester, which can supply the DUT with unlimited pseudo-random patterns created autonomously by the MCU firmware from any selected seed. The tester prototype developed to collect experimental results includes a low-cost System-on-Chip based on a multi-core MCU and a set of peripheral cores, encompassing timers and Direct Memory Access modules. The tester prototype is used to stress an automotive chip accounting for about 20 million gates, 700 thousand scan flip-flops, and several scan modes. The combination of pseudo-random pattern generation with the ability to control different scan and Design for Testability (DfT) modes, including LBIST, permits to reach a higher coverage of stress metrics than by the application of a limited set of pre-computed ATPG patterns. The toggle coverage level reached is up to 95.89%. The application speed achieved by the tester with non-optimized connections is up to about 10MHz.

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“…Such a clock is kept stable at the logic value '0' to maintain a static state for a defined amount of time. We named such a measurement as neighborhoodoriented static stress metric [14].…”

Section: Stress Evaluation Metricsmentioning

confidence: 99%

Section: Pattern Generation Flowmentioning

confidence: 99%

mentioning

confidence: 97%

mentioning

confidence: 99%

See 2 more Smart Citations

A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

Bernardi

Appello

Bertani

et al. 2023

IEEE Trans. Comput.

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“…In our production flow, we evaluate the following BI stress metrics [12], [13]: -Extended statistics. We compute the number of times a node toggles during the simulation, along with the values assumed by the nodes on each time frame.…”

Section: B Test and Burn-in Related Stress Metricsmentioning

confidence: 99%

Parallel Multithread Analysis of Extremely Large Simulation Traces

Appello,

Bernardi,

Calabrese

et al. 2022

IEEE Access

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With the explosion in the size of off-the-shelf integrated circuits and the advent of novel techniques related to failure modes, commercial Automatic Test Pattern Generator and fault simulation engines are often insufficient to measure the coverage of particular metrics. Consequently, a general working framework consists of storing simulation traces during the analysis phase and collecting test statistics from post-processing. Unfortunately, typical simulation traces can be hundreds of gigabytes long, and their analysis can require several days, even on large and powerful computational servers. In this paper, we propose a set of strategies to mitigate the evaluation time and the memory needed to analyze huge dump files stored in the standard Value Change Dump format. We concentrate on burn-in-related metrics that current commercial fault simulators and Automatic Test Pattern Generators cannot evaluate. We show how to divide the analysis process into several concurrent pipeline stages. We revise the logic process of each stage and all principal intermediate data structures, to adopt smart parallelization with very low contention and extremely low overhead. We exploit several low-level optimizations from modern programming techniques to reduce computation time and balance the different pipeline phases. We analyze simulation traces up to almost 250 GBytes computing different testing metrics. Overall, we can keep under control the memory usage, and we show time improvements of over two orders of magnitude compared to previously adopted state-of-the-art tools.

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