Injecting FPGA Configuration Faults in Parallel

Abstract

When using SRAM-based FPGA devices in safetycritical applications testing against bitflips in the device configuration memory is essential. Often such tests are achieved by corrupting configuration memory bits of a running device, but this has many scalability, reliability, and flexibility challenges. In this paper, we present a framework and a concrete implementation of a parallel fault injection cluster that addresses these challenges. Scalability is addressed by using multiple identical FPGA devices, each testing a different region in parallel. Reliability is addressed by using reconfigurable system-on-chip devices, that are isolated from each other. Flexibility is addressed by using a pendingcommit structure, that continually checkpoints the overall experiment and allows elastic scaling. We test and showcase our approach by exhaustively flipping every bit in the configuration memory of the CHStone benchmark suite and a VivadoHLS generated k-means clustering image processing application. Our results show that: linear scaling is possible as the number of devices increases; the majority of error inducing bitflips in the k-means application do not significantly impact the output; and that the Xilinx Essential bits tool may miss some bits that can induce errors.

Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs

“…Several fault injection frameworks have been proposed in the last decades; recent examples, compliant with modern device families are [8]- [11]. Their architecture is pretty standard; it is based on the FPGA internal memory configuration interface that is exploited to emulate an SEUs, directly accessed by custom modules or by the Xilinx SEM Intellectual Property (IP), and a controller to coordinate the execution of the fault injection campaign on a Design Under Test (DUT).…”

“…Their architecture is pretty standard; it is based on the FPGA internal memory configuration interface that is exploited to emulate an SEUs, directly accessed by custom modules or by the Xilinx SEM Intellectual Property (IP), and a controller to coordinate the execution of the fault injection campaign on a Design Under Test (DUT). These fault injectors are employed to evaluate the robustness of image processing applications (or part of them), such as a Convolutional Neural Network (CNN) [9], an image compression algorithm [10] or a K-means image clustering one [11]. In the reported experiments, outputs are analyzed in a more advanced way than the classical taxonomy (no-effect, crash/timeout, silent data corruption) by using image quality metrics (such as the SSIM in [10], [11]).…”

“…These fault injectors are employed to evaluate the robustness of image processing applications (or part of them), such as a Convolutional Neural Network (CNN) [9], an image compression algorithm [10] or a K-means image clustering one [11]. In the reported experiments, outputs are analyzed in a more advanced way than the classical taxonomy (no-effect, crash/timeout, silent data corruption) by using image quality metrics (such as the SSIM in [10], [11]). In fact, the aim of these approaches is to accurately analyze how disruptive the fault is on the produced output.…”

“…To pursue such strategy, it is necessary to analyze the effects of the faults occurring in the underlying hardware platform on the behaviour of the application itself. The current best practice, based on circuit-level fault injection, allows for an accurate reliability analysis, but it requires the overall system to be fully implemented and deployed on an FPGA device [8]- [11]. This represents a relevant limitation due to the time to design a hardware component, thus not allowing to provide a fast and early feedback to the hardening process before the final implementation and deployment on the FPGA device.…”

Dependability-driven Strategies to Improve the Design and Verification of Safety-Critical HDL-based Embedded Systems

“…For instance, the proposal in [80] speeds up the SBFI campaigns by scheduling the simulations on a network of workstations and combining such approach with checkpointing in order to reduce the warm-up time of each simulation to the strict minimum. The proposal in [56] relies on a stack of FPGA boards to execute FFI experiments in parallel, thus the reduction of experimental time is related to the number of FPGA boards available for experimentation. Some works also propose the development of specialized fault simulators, like the one proposed in [119] for IcarusVerilog models.…”