Initial Performance Evaluation of the NetEffect 10 Gigabit iWARP Adapter

Dalessandro, D.; Wyckoff, P.; Montry, G.

doi:10.1109/clustr.2006.311915

Cited by 17 publications

(4 citation statements)

References 7 publications

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“…If the RDMA flow control credits of a connection are used up without being released by the receiver, the communication falls back on the Send/Receive channel. Some work has also looked at the cost of memory registration in RDMA-enabled networks, especially its high costs for small buffers [11,23]. In a recent work presented in [24], researchers have proposed a pinning model in Open-MX based on the decoupling of memory pinning from the application, as a step toward a reliable pinning cache in the kernel.…”

Section: Related Workmentioning

confidence: 98%

Exploiting application buffer reuse to improve MPI small message transfer protocols over RDMA-enabled networks

Rashti

Afsahi

2011

Cluster Comput

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To avoid the memory registration cost for small messages in MPI implementations over RDMA-enabled networks, message transfer protocols involve a copy to intermediate buffers at both sender and receiver. In this paper, we propose to eliminate the send-side copy when an application buffer is reused frequently. We show that it is more efficient to register the application buffer and use it for data transfer. The idea is examined for small message transfer protocols in MVAPICH2, including RDMA Write and Send/Receive based communications, one-sided communications and collectives. The proposed protocol adaptively falls back to the current protocol when the application does not frequently use its buffers. The performance results over InfiniBand indicate up to 14% improvement for single message latency, close to 20% improvement for one-sided operations and up to 25% improvement for collectives. In addition, the communication time in MPI applications with high buffer reuse is improved using this technique.

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Section: Related Workmentioning

confidence: 98%

Exploiting application buffer reuse to improve MPI small message transfer protocols over RDMA-enabled networks

Rashti

Afsahi

2011

Cluster Comput

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“…The most common Type 1 implementations in the research community are open source Open-iSCSI [6] and UNH-iSCSI projects [10]. Examples of Type 2 are ASIC-based 10 GbE TOEs: Chelsio's Terminator 3 chip [11] and NetEffect's NE010 adapter [12]. Both adapters show low CPU utilization and near 10 Gbps performance, especially for larger data sizes.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of IP-based iSCSI Offload Engine on an FPGA

Akagić¹,

Amano²

2013

IPSJ Transactions on System LSI Design Methodology

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The IP-based storage systems often require bandwidth intensive access to storage devices, thus they exhibit high CPU utilization and low throughput when executed in a principally software implementation. This is especially evident for multi-Gbps networks where the impact of computational overhead is so pronounced that the current state of the art processors cannot take advantage of the capacity of the network. In this paper we propose new iSCSI Offload Engine architecture for high data rate storage networking. Based on our analysis of open source Open-iSCSI initiator, we offload the most computationally intensive and the most executed functions in a common case scenario, while other functions are implemented in a modified Open-iSCSI initiator on a general purpose processor. Our architecture overcomes the performance limitations imposed by a single processor which runs on 15x higher operating frequency than our accelerator. It exhibits very low CPU utilization of approximately 3% on the host CPU, which is 10-15x reduction compared with software implementation. The maximum transmission throughput is 7.81 Gbps, while reception throughput is 7.34 Gbps, which is 2 times speedup over software. The new architecture also shows comparable performance with Chelsio T110 ASIC-based HBA, and has more flexibility.

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“…Currently, 10 GBit/s networking capability is supported by a number of commercial products, with a range of interconnect technologies. Specific examples include: (1) 10GbE offerings from Myricom [4] and Chelsio [2], (2) traditional cluster-interconnect technologies from Myricom [7] and Quadrics [24,23], and (3) interconnects based on the Infiniband standards [1] from Mellanox [3], NetEffect [9], and other vendors. [15] presents a representative performance comparison of such interconnects.…”

Section: Introductionmentioning

confidence: 99%

Optimization and bottleneck analysis of network block I/O in commodity storage systems

Marazakis

Papaefstathiou

Bilas

2007

Proceedings of the 21st Annual International Conference on Supercomputing

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Building commodity networked storage systems is an important architectural trend; Commodity servers hosting a moderate number of consumer-grade disks and interconnected with a high-performance network are an attractive option for improving storage system scalability and cost-efficiency. However, such systems incur significant overheads and are not able to deliver to applications the available throughput. We examine in detail the sources of overheads in such systems, using a working prototype to quantify the overheads associated with various parts of the I/O protocol. We optimize our base protocol to deal with small requests by batching them at the network level and without any I/O-specific knowledge. We also redesign our protocol stack to allow for asynchronous event processing, in-line, during send-path request processing. These techniques improve performance for a 8-disk SATA RAID0 array from 200 to 290 MBytes/s (45% improvement). Using a ramdisk, peak performance improves from 320 to 474 MBytes/s (48% improvement), which is 72% of the maximum possible throughput in our experimental setup. We also analyze the remaining system bottlenecks, and find that although commodity storage systems have potential for building high-performance I/O subsystems, traditional network and I/O protocols are not fully capable of delivering this potential.

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Initial Performance Evaluation of the NetEffect 10 Gigabit iWARP Adapter

Cited by 17 publications

References 7 publications

Exploiting application buffer reuse to improve MPI small message transfer protocols over RDMA-enabled networks

Exploiting application buffer reuse to improve MPI small message transfer protocols over RDMA-enabled networks

Design and Implementation of IP-based iSCSI Offload Engine on an FPGA

Optimization and bottleneck analysis of network block I/O in commodity storage systems

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