InGaAs/InP DHBT technology and design methodology for over 40 Gb/s optical communication circuits

André, Ph.; Blayac, S.; Berdaguer, P.; Benchimol, J.L.; Godin, J.; Kaffmann, N.; Konczykowska, A.; Kasbari, Abed-Elhak; Riet, M.

doi:10.1109/4.944658

Cited by 18 publications

(6 citation statements)

References 10 publications

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“…The low operation speed and the small eye opening of the fabricated circuit compared with the simulation result are due to parasitic effects such as the loading effect of the output buffer, signal reflection due to impedance mismatch, and layout parasitic effects. To improve the speed, optimization of the output buffer and layout for very high-speed integrated circuits (VHSICs) 8) is clearly needed. Figure 9 shows the power dissipation of the core circuit of the proposed NRZ D-F/F (solid line), the MOBILE-based RZ D-F/F (dash line), and the MOBILE-based NRZ D-F/F (dash-dot line) according to operating bit rate.…”

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

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High-Speed and Low-Power Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology

Kim¹,

Yeon²,

Seo³

2007

jjap

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A high-speed and low-power delayed flip-flop circuit with non-return-to-zero mode output using a new negative differential resistance logic element is proposed and fabricated using resonant tunneling diode (RTD)/high electron mobility transistor (HEMT) integration technology on an InP substrate. The number of devices used in the delayed flip-flop and the power dissipation has been significantly reduced by using the proposed scheme. The operation of the fabricated delayed flip-flop is demonstrated up to 26 Gb/s with a very low power dissipation of about 2.8 mW at a power supply voltage of 0.9 V.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

High-Speed and Low-Power Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology

Kim¹,

Yeon²,

Seo³

2007

jjap

View full text Add to dashboard Cite

show abstract

“…The low operation speed and the small eye opening of the fabricated circuit compared with the simulation result are due to parasitic effects such as the loading effect of the output buffer, signal reflection due to impedance mismatch, and layout parasitic effects. To improve the speed, optimization of the output buffer and layout for very high-speed integrated circuits (VHSICs) [10] is clearly needed. This increased power dissipation results from the increased power dissipation when the clock is low.…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

New NRZ-mode resonant tunneling bistable-to-monostable-to-bistable transition logic element operating up to 36 Gb/s

Kim

Yeon

Seo

2007

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

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In this paper, we present new resonant tunneling bistable-to-monostable-to-bistable transition logic element with non-return-to-zero (NRZ) mode output. The proposed circuit is composed of resonant tunneling diode (RTD)/high electron mobility transistor (HEMT) series connection (RHS) and RTD/HEMT parallel connection (RHP). Novel high-speed and low-power NRZ delayed flip-flop (D-F/F) operation has been successfully achieved using RTD/HEMT integration technology on an InP substrate. The operation of the fabricated circuit was confirmed up to 36 Gb/s with a very low power dissipation of about 3 mW at a power supply voltage of 0.9 V.

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“…Methods have been developed to extract and to include the more critical interconnections in postsimulations [7]. However, due to the high-speed circuits complexity, it is not possible for a full-custom circuit design to extract each parasitic element of the layout.…”

Section: Introductionmentioning

confidence: 99%

Improved Design and Characterization Method for Very High Speed Bipolar Circuits

Kasbari

Ouslimani

Blayac³

et al. 2008

2008 Global Symposium on Millimeter Waves

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An improved design method for high speed bipolar circuits is presented. It uses iso base-collector capacitance curves superposed to the duty cycles plots in the (Ic,Vce) plane. This new optimization way gives the optimum operating region for each transistor of a bipolar circuit to reach the best trade-off between the switching speed and the power consumption. Electrical design of emitter-coupled pair, which constitutes the basis of EmitterCoupled Logic (ECL) circuits, is detailed to explain the design method. Each part of the measurement set-up is characterized in time and frequency domains to improve the measurement method. These improvements have enabled the design and characterization of InP double-heterojunction-bipolar transistor master-slave D-type flip-flop circuits. 40Gb/s measurement with more than 85 % eye-diagram opening validates this method.

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InGaAs/InP DHBT technology and design methodology for over 40 Gb/s optical communication circuits

Cited by 18 publications

References 10 publications

High-Speed and Low-Power Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology

High-Speed and Low-Power Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology

New NRZ-mode resonant tunneling bistable-to-monostable-to-bistable transition logic element operating up to 36 Gb/s

Improved Design and Characterization Method for Very High Speed Bipolar Circuits

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