Influence of transmission-line interconnections between gigabit-per-second ICs on time jitter and instabilities

Hauenschild, J.; Rein, H.-M.

doi:10.1109/4.102673

Cited by 32 publications

(5 citation statements)

References 5 publications

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“…This is not a feasible solution, due to the effect of pad capacitances and long bond wires. The best solution is usually to include an approximate on-chip input matching network at 50 , regardless of the imaginary part of the input impedance: this is found to be very effective in suppressing the effects of input bond wire inductance on time jitter and oscillations [6].…”

Section: Input Matchingmentioning

confidence: 99%

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Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

Centurelli¹,

Pallotta

Tommasino

et al. 2006

Analog Integr Circ Sig Process

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The diffusion of optical communication systems in the access network and for short-haul datacom applications requires the use of low-cost plastic packages: the functional block most affected is the limiting amplifier, that is often the first stage of the Clock and Data Recovery (CDR) IC.In this paper we illustrate the design issues of the input-matching and offset-cancelling network for a differential limiting amplifier for optical communication systems, with particular emphasis on the effect of bond wires. We discuss the limitations of passive feedback networks when used both for offset suppression and for input matching, and propose a topology that overcomes such limitations by using an active feedback loop. A 50 -loaded differential pair is used to achieve input matching and high offset suppression, and its buffering action desensitizes the input matching from the effect of the bond wires connecting off-chip filtering capacitors. Very good performance even with low cost plastic packages can be achieved by solving the trade-off between power consumption, offset suppression and the value of the low-pass filtering capacitors.Design examples of CDR IC's for 2.5 Gb/s optical systems are presented to compare the proposed topology with solutions based on passive feedback networks.

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Section: Input Matchingmentioning

confidence: 99%

“…In this Section we propose a topology to achieve offset suppression and input matching [10], based on an active dc feedback loop similar to the one presented in [11] and the classical input matching scheme for CML inputs [6], as shown in Fig. 4.…”

Section: Active Offset-cancelling Networkmentioning

confidence: 99%

Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

Centurelli¹,

Pallotta

Tommasino

et al. 2006

Analog Integr Circ Sig Process

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“…In this case, as shown in Fig. Therefore, double reflexions may occur which increase time jitter [5]. Due to the bond inductance and the non-linear and frequency dependent impedance of LD the line matching is not exact.…”

Section: Block Diagram Of the Driver Circuit Andmentioning

confidence: 99%

“…At the inputs, on-chip resistors (Κ, = 50Ω) are used which ensure good transmission line matching and absolute input stability [5].…”

Section: Block Diagram Of the Driver Circuit Andmentioning

confidence: 99%

Design of a Silicon Bipolar Laser- and Line-Driver IC with Adjustable Pulse Shape and Amplitude for Data Rates Around and Above 10 Gbit/s

Rein¹

1992

Frequenz

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The design of a very-high-speed versatile laser-and line-driver 1C in silicon bipolar«technology is described. The most important aim is to show how to obtain an optimum (symmetrical) output pulse shape in a wide range of operating speed and output current swing, despite the fact that single-ended operation is applied at both the input and output. This task is solved by using a two-stage circuit concept which allows to optimally adjust two important internal offset voltages and, if required, an internal voltage swing via external potentiometers. These adjustments are independent of the operating speed and virtually also of the (easily controllable) output current swing. Finally, it is demonstrated by simulation that with advanced silicon bipolar technologies laser drivers for 10 Gbit/s optical-fiber transmission systems can be realized.Übersicht: Der Entwurf eines sehr schnellen und vielseitigen Laser-und Leitungstreibers in Silizium-Bipolar-Technologie wird beschrieben. Das wichtigste Ziel der Arbeit ist zu zeigen, wie man trotz Eintaktbetrieb eine optimale (symmetrische) Impulsform am Ausgang erreichen kann, und zwar in einem weitenBereich der Datenrate und des Ausgangshubs. Diese Aufgabe läßt sich durch ein zweistufiges Schaltungskonzept lösen, bei dem zwei wichtige interne Offset-Spannungen und, falls erforderlich, ein interner Spannungshub über externe Potentiometer eingestellt werden können. Die optimale Einstellung ist unabhängig von der Datenrate und weitgehend auch von dem (leicht einstellbaren) Ausgangshub. Schließlich wird durch Simulation gezeigt, daß mit fortschrittlichen Silizium-Bipolar-Technologien Lasertreiber für Glasfaser-Übertragungssysteme mit Datenraten von 10 Gbit/s realisierbar sind. Für die Dokumentation: Schnelle Silizium-Schaltungen / Lasertreiber / digitale Treiberstufen / Pulsformung

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“…They are power utilization, speed, silicon territory, and the ring oscillator's delay is a shunt circle. The circuit must fulfill the Barkhausen criterion, which measures to give the oscillation and support the circuits to increase the voltage [13]. It must have the move around a stage of 2π.…”

Section: Introductionmentioning

confidence: 99%

Datasets design of gate diffusion input based pipeline architecture for numerically controlled oscillator

Gujjula

Perumal

Kodali

et al. 2022

IJEECS

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<span lang="EN-US">Gate diffusion input (GDI) is a technique, which enables reducing power consumption, area and delay in the digital circuits significantly, at the same time maintains low complexity of the logical design. This paper focuses on the analysis and interpretation of the design and implementation of GDI-based pipeline architecture for numerically controlled oscillator (NCO) using look up table (LUT). Based on the input signal and the alternate signal, this phase separation will separate the phase difference signal. The NCO generates a frequency and phase harmonized output signal with an antecedence fixed frequency clock. The 32-bit counter then compares the current count to the value stored in the compare register. Here the Coherent control comes into picture. It controls the carrier synchronizer by employing data from the 32-bit counter and the obtained data will be saved. It is updated and advanced using the third peer group of frequency synthesis technology. The test outcomes are accompanied with the theoretical concept and reproduced the results. The main objective of GDI-based pipeline architecture for NCO using LUT is to reduce the usage of metal oxide semiconductor field effect transistors (MOSFET’s). NCO is an indispensable component in many digital communication systems linked to modems, software-defined radios, and digital radio, digital down/upconverters for cellular and personal communications service base stations.</span>

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Influence of transmission-line interconnections between gigabit-per-second ICs on time jitter and instabilities

Cited by 32 publications

References 5 publications

Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

Design of a Silicon Bipolar Laser- and Line-Driver IC with Adjustable Pulse Shape and Amplitude for Data Rates Around and Above 10 Gbit/s

Datasets design of gate diffusion input based pipeline architecture for numerically controlled oscillator

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