Influence of starting material on analog technology fabrication yield and device component performance

Abstract

Development of high-performance fully depleted silicon-on-insulator based extended-gate field-effect transistor using the parasitic bipolar junction transistor effect Appl. Phys. Lett. 101, 133703 (2012); 10.1063/1.4757000Integration of strained and relaxed silicon thin films on silicon wafers via engineered oxide heterostructures: Experiment and theory J. Appl. Phys. 108, 073526 (2010); 10.1063/1.3486217 Ion dose, energy, and species dependencies of strain relaxation of SiGe buffer layers fabricated by ion implantation techniqueChoice of substrate used for analog complementary metal-oxide-semiconductor ͑CMOS͒ technologies impacts device performance and fabrication yields significantly. This study examines the impact of low-angle ͑Ͻ5°͒ off-axis Si͑100͒ substrate rotated around ͗110͘ axis and 0°Si͑100͒ on-axis starting material on inline process control, parametric device performance, and ultimately fabrication yields. The interaction of thermal processes and silicon epitaxial growth process variation on inline photoalignment and its influence on device design and performance is discussed for both types of substrates. The device components include 3 and 5 V analog CMOS, lateral p-n-p bipolar transistor, junction field effect transistors, and drain extended transistors, DENMOS and DEPMOS, where the drain extensions are formed using well implants. The necessity to reintegrate silicon epitaxial growth, well photolithography and implants, Vt implants, and gate oxide process loop to accommodate substrate crystal orientation changes will be presented. A novel front-end-of-the-line integration scheme to improve interwafer and intrawafer electrical distributions with excellent transistor matching and 1 / f noise performance for aforementioned device components will also be discussed in this context.