Influence of soft breakdown on NMOSFET device characteristics

Pompl, T.; Wurzer, H.; Kerber, M.; Wilkins, R.C.W.; Eisele, I.

doi:10.1109/relphy.1999.761596

Cited by 54 publications

(25 citation statements)

References 8 publications

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“…Weir et al [99] concluded that there was no significant degradation observed in the transistor parameters and following soft breakdown and indicated that perhaps only analog circuitry would be affected by an increased gate current noise. Similar findings were reported on the effect of soft breakdown on transistor performance if the breakdown spot was not located in the device's source or drain region [103], [106], [107]. It was shown in [106] that hard breakdown and catastrophic device failure occurred more frequently as the channel length of the device was decreased.…”

Section: ) Device-level Failuresupporting

confidence: 82%

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Ultrathin gate oxide reliability: physical models, statistics, and characterization

Suehle

2002

IEEE Trans. Electron Devices

144

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Abstract-The present understanding of wear-out and breakdown in ultrathin ( 5 0 nm) SiO 2 gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed.

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Section: ) Device-level Failuresupporting

confidence: 82%

“…used [103]- [105]. The process of periodically interrupting stress did not effect the failure time of the devices [103], [104].…”

Section: B Soft-breakdown Detection Techniquesmentioning

confidence: 99%

Ultrathin gate oxide reliability: physical models, statistics, and characterization

Suehle

2002

IEEE Trans. Electron Devices

144

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“…It was therefore suggested that SBD would not cause device or circuit failure in many applications [146]. However, Pompl et al [194] and others [135], [138], [195], [196] later showed that SBD will cause a significant increase in the transistor-off current if the breakdown spot is in the drain region, which is increasingly likely in short-channel devices. This will be referred to as "device breakdown."…”

Section: B Device Breakdownmentioning

confidence: 99%

“…In a study of the channel length-and width-dependence of device breakdown in n-FETs stressed at 4.1 V, Wu [135], [177] showed that, for short-channel devices (0.2-m channel length), the distribution of oxide breakdown times for the first breakdown event coincides with the distribution of device breakdown times, whereas for longer channels (10 m) the device breakdown occurs some time after the first soft breakdown. After a "hard" breakdown, the device is clearly nonfunctional by any ordinary criterion, exhibiting a negative drain current when the gate-to-drain leakage exceeds the normal transistor on current [194]. However, even a hard breakdown may not completely destroy circuit functionality: Kaczer et al [197] showed that in some cases a circuit may be able to survive an oxide breakdown that previously would have been assumed to be catastrophic.…”

Section: B Device Breakdownmentioning

confidence: 99%

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

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“…5). A shift of I GIDL (DI GIDL ) indicates the generation of Q ox at the gate-drain overlap region because Q ox increases I GIDL by increasing the surface potential of the drain [14]. Rauch III et al reported simulation results showing that the gate-drain overlap region is where EES contributes most to HC degradation [5].…”

Section: Resultsmentioning

confidence: 99%

Effect of electron–electron scattering at an elevated temperature on device lifetime of nanoscale nMOSFETs

Lee¹,

Kim²,

Kim³

et al. 2012

Microelectronics Reliability

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Influence of soft breakdown on NMOSFET device characteristics

Cited by 54 publications

References 8 publications

Ultrathin gate oxide reliability: physical models, statistics, and characterization

Ultrathin gate oxide reliability: physical models, statistics, and characterization

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Effect of electron–electron scattering at an elevated temperature on device lifetime of nanoscale nMOSFETs

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