Influence of post-deposition annealing in oxygen ambient on metal–organic decomposed CeO2 film spin coated on 4H-SiC

Comparison of metal-organic decomposed (MOD) cerium oxide (CeO2) gate deposited on GaN and SiC substrates

“…At low electric field (Eo2.8 MV/cm), 1150 1C annealed CeO 2 /SiC sample demonstrated a lower leakage current when compared [17], (b) CeO 2 /SiC [16], and (c) 1150 1C annealed CeO 2 /SiC [16] samples with insets of two-dimensional AFM topographies of the respective samples. [16] as well as 1000 1C annealed CeO 2 /GaN sample [17].…”

“…The utilization of CeO 2 may suppress the electric field imposed in the gate oxide by a factor of (3.9/k) when compared with SiO 2 . Previously, metalorganic decomposed (MOD) CeO 2 annealed in oxygen ambient has been spun-coated as gate oxide in the fabrication of SiC- [16] and GaN-based [17] MOS structures. During post-deposition annealing (PDA), an interfacial layer of SiO 2 and b-Ga 2 O 3 has been formed in CeO 2 /SiC [16] and CeO 2 /GaN [17] systems annealed at 1000 1C, respectively.…”

“…Previously, metalorganic decomposed (MOD) CeO 2 annealed in oxygen ambient has been spun-coated as gate oxide in the fabrication of SiC- [16] and GaN-based [17] MOS structures. During post-deposition annealing (PDA), an interfacial layer of SiO 2 and b-Ga 2 O 3 has been formed in CeO 2 /SiC [16] and CeO 2 /GaN [17] systems annealed at 1000 1C, respectively. A better MOS characteristic in term of dielectric breakdown field has been demonstrated by CeO 2 /GaN system [17] when compared with CeO 2 /SiC system [16].…”

“…During post-deposition annealing (PDA), an interfacial layer of SiO 2 and b-Ga 2 O 3 has been formed in CeO 2 /SiC [16] and CeO 2 /GaN [17] systems annealed at 1000 1C, respectively. A better MOS characteristic in term of dielectric breakdown field has been demonstrated by CeO 2 /GaN system [17] when compared with CeO 2 /SiC system [16]. However, PDA at 1000 1C has posed a crucial concern, wherein decomposition of GaN surface has led to cracking of GaN surface [18].…”

“…However, PDA at 1000 1C has posed a crucial concern, wherein decomposition of GaN surface has led to cracking of GaN surface [18]. This issue is not encountered by the CeO 2 /SiC system as SiC substrate is able to sustain a higher PDA temperature, up to 1150 1C [16]. In this paper, a thorough comparison on the physical and electrical characteristics of CeO 2 gate oxide incorporated in both SiC-and GaN-MOS structures has been presented.…”