Influence of Interface States on Output Characteristics of 4H-SiC MESFETs on Semi–Insulating Substrates

Abstract

The aim of this work is to study the origin of parasitic phenomena in the output characteristics of 4H-SiC MESFETs on semi-insulating (SI) substrates with various buffer layers. Ids-Vds measurements as a function of temperature have first been performed. Different parasitic effects such as kink effect, hysteresis effect when the gate voltage is successively increased or decreased, or changes in the output characteristics after a high drain polarization are presented. Random Telegraph Signal (RTS) measurements and frequency dispersion of the output conductance have next been realized. From the obtained results, we propose that the parasitic effect on the output characteristics are correlated with the presence of deep levels located near the semi -insulating substrate interface. The main observed trap is tentatively attributed to the presence of Vanadium in the SI substrate.

Development of Field-Effect Transistor-Type Photorewritable Memory Using Photochromic Interface Layer

“…Similarly to OFET, such a hysteresis behavior of output characteristics can be generally explained by interfacial deep trap levels at semiconductor/ insulator interfaces for inorganic transistors. 17,18) On the other hand, output characteristics of FET ORI (open-ring isomer the right-side graph) do not show such a hysteresis behavior. Therefore, it is clear that the HOMO level of the open-ring isomer would not work as a deep trap level.…”

Trapping effects in GaN and SiC microwave FETs

“…This behavior was associated with an increase in trap-filling as the drain voltage swing was increased. The nonlinear model was applied [7] to optimize the buffer layer between the SI substrate and the active layer, such that carrier injection at high bias was minimized or eliminated. Measurements were carried out on several devices grown with varying buffer layer thickness and doping.…”

“…Measurements were carried out on several devices grown with varying buffer layer thickness and doping. It was reported [7] that channel carrier injection was successfully reduced or eliminated by this procedure, although no information about the optimized device was provided, for proprietary reasons. Additionally, the conductance dispersion was studied as a function of temperature in order to extract trap parameters.…”

Defects in SiC

“…However, as found recently, SiC MESFETs using heavily vanadium-doped SI substrates have a great problem with carrier trapping to deep level centers, leading to drain current collapse and instability of MESFETs [22]. This creates the interest of replacing vanadium by intrinsic defects.…”