Influence of Channel Thickness on Analog and RF Performance Enhancement of an Underlap DG AlGaN/GaN based MOS-HEMT Device

Roy, Akash; Mitra, Rajrup; Kundu, Atanu

doi:10.1109/devic.2019.8783865

Cited by 15 publications

(5 citation statements)

References 14 publications

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“…This architecture is beneficial in achieving better ON/OFF current ratios, which are crucial for low power applications. The 10nm scale SDG TFET leverages tunneling as its fundamental mechanism of operation (20). The symmetrical gates help in optimizing tunneling processes, ensuring reliable and efficient charge through the channel and this 10nm SDG TFET is to enhance power efficiency.…”

Section: Device Structure and Simulation Parametersmentioning

confidence: 99%

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Buttol,

Balaji,

Srinivasa Rao

2024

IJE

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In this work, a Symmetrical Dual Gate Tunnel Field Effect Transistor (SDGTFET) is proposed with gate dielectric materials in 10nm technology. The electrical performance parameters of this proposed device are investigated using technology computer aided design (TCAD) simulator. The new SDGTFET employing with high-k dielectric material such as hafnium oxide (HfO2) and interfacial layer (IL). The 2nm HfO2 with 30 dielectric constant is used between the interfacial layer and the metal gate on both sides of the device. The variation of the drain current with the varying of gate length, effective gate materials and effective oxide layer thickness of the device is evaluated in this work. By optimizing the proposed device with gate dielectric material the on current gets ∼4.2 times enhanced and the averaged subthreshold swing (SSavg) becomes reduced from 90.2 mV/dec to 53.8 mV/dec. Therefore, the SDGTFET structure has better performance than single material and double material TFET and shows a lower ambipolar current and a better on current to off current ratio.

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Section: Device Structure and Simulation Parametersmentioning

confidence: 99%

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Buttol,

Balaji,

Srinivasa Rao

2024

IJE

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show abstract

“…Power efficiency is a critical concern in modern semiconductor design. The analysis delves into the power consumption patterns of DMG FinFETs under various operating conditions being dynamic power consumption during switching events and static power dissipation in idle states (20). This work investigates the robustness of DMG FinFETs in the face of process variations and environmental factors, providing insights into their longterm performance related to low-K dielectric materials and high-K dielectric materials such as SiO2, HfO2 and TiO2 (21).…”

Section: Introductionmentioning

confidence: 99%

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Padmaja,

Vemana Chary,

Erigela

et al. 2024

IJE

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A High-K Dielectric Dual Metal Gate FinFET (DMG-FinFET) is proposed in this work to improve the drain current and electrical characteristics of the device. The proposed device employing dielectric materials such as Silicon dioxide, Hafnium oxide and Titanium oxide and investigated in 10 nm technology. The architecture represents a critical advancement in transistor design, addressing challenges posed by traditional high-K gate dielectric materials being HfO2 and TiO2. This work employs a comprehensive approach, incorporating simulation techniques to evaluate the performance metrics of DMG FinFET. This investigation encompasses key aspects being transistor characteristics, power consumption, and reliability. This high-k dielectric (HfO2) Dual material Gate -FinFET device achieving improved performance parameters such as Ion= 32.12 mA, Ioff= 33 μA, Gm(max) = 0.045 S, Gds(max) = 0.024 S and Ron(max) = 32.87 kΩ. Therefore this work is suitable for designing high performance devices with high-k dielectric materials being HfO2 and TiO2. The impact of dual metal gate materials on Ion, Ioff, Gm (max), Gds(max) and Ron(max) is calculated and improved 64% compared to conventional device.

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“…Each material is chosen for its unique properties and compatibility with the device's operation. This dual-gate design allows for precise control of the electric field within the transistor channel (20).…”

Section: Introductionmentioning

confidence: 99%

Gate Oxide Thickness and Drain Current Variation of Dual Gate Tunnel Field Effect Transistor

Howldar,

Balaji,

Srinivasa Rao

2024

IJE

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Influence of Channel Thickness on Analog and RF Performance Enhancement of an Underlap DG AlGaN/GaN based MOS-HEMT Device

Cited by 15 publications

References 14 publications

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Gate Oxide Thickness and Drain Current Variation of Dual Gate Tunnel Field Effect Transistor

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