Influence of capacitive effects on the dynamic of a CNTFET by Monte Carlo method

d'Honincthun, H. Cazin; Nguyen, Huu-Nha; Galdin‐Retailleau, S.; Bournel, A.; Dollfus, Philippe; Bourgoin, Jean‐Philippe

doi:10.1016/j.physe.2007.12.004

Cited by 11 publications

(3 citation statements)

References 25 publications

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“…Figure 2 shows the geometry of GAA CNTFET modeled by Silvaco's ATLAS 3D tool, which uses a single CNT as a channel with gate wrapped around the channel to provide complete control over the flow of charge carriers through the channel as ballistic transport. The High_K gate dielectric materials have been used in CMOS process and FinFETs [24][25][26], the same concept of equivalent oxide thickness is used here to overcome gate tunneling which causes leakage through the dielectric layer and palladium as gate and source/drain contact materials due to its better wettability and compatibility with other material layers in the CNTFET device structure [13,27]. The palladium as conductor for source/drain/gate contacts, heavily doped source/drain n +regions with donor concentration of 1e+20 /cm 3 for ohmic contacts and SiO 2 -HfO 2 stack as gate dielectric material to provide better gate coupling without increase in gate tunneling current for optimum device performance and leakage reduction has been used to model and simulate GAA CNTFET for robust applications.…”

Section: Simulation and Estimation Of Band Gap And Density Of States mentioning

confidence: 99%

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

Singh

Prasad

Kumar

2020

Mater. Res. Express

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The device dimensions have been consistently scaling down since many developing technologies need smaller and faster integrated circuits for advancement and improvement in both performance and device density. Device dimensions have been decreased drastically from micron to sub nanometer regime. Traditionally, miniaturizing and performance improvement was obtained by tweaking the MOSFET-reducing the channel lengths and gate oxide thickness, increasing dielectric constants etc Unfortunately at 22 nm node it reached a dead end. However, at 22 nm node the tri-gate FinFET introduced by Intel Corporation have provided many possibilities for scaling the dimensions with satisfactory device performance. Further, the gate all around (GAA) carbon nano tube field effect transistor (CNTFET) provides high gain, high trans-conductance, reduced short channel effects and conditions for scaling the technology to sub nano scale. Due to surround gate structure this GAA CNTFET offers better control with integration of high_k stacked dielectric wrapped around the channel. In this paper, first properties of Carbon nanotube (CNT) have been comprehensively studied for various chirality and diameter and parameters viz. Density of States (DoS) and Band gap (E g ) are extracted by using MedeA tool's VASP 5.3 module. The various CNT chirality have been optimized and the extracted parameters used to model and simulate CNTFET using Silvaco's Devedit3D, Atlas and Atlas3D modeling and simulation modules. The device input (I D -V GS ) and output (I D -V DS ) characteristics have been intensively studied and parameters including I ON /I OFF ratio, DIBL, sub threshold slope extracted and compared with the conventional devices. The GAA CNTFET device at 0.8 V supply voltage exhibits threshold voltage (V TH ) 0.254 V, drain induced barrier lowering (DIBL) 72 mV/V, sub-threshold swing (SS) 63.29 mV/dec, and I ON/ I OFF ratio 7.17e+06. The results demonstrate improvement in device parameters for the GAA CNTFET device as compared to bulk silicon and FinFET devices.

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Section: Simulation and Estimation Of Band Gap And Density Of States mentioning

confidence: 99%

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

Singh

Prasad

Kumar

2020

Mater. Res. Express

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“…Thus even with a reduced oxide thickness we can expect a reduced gate capacitance because of inverse and logarithmic relationship. However, too much thin gate insulator will cause excessive leakage and so it is properly balanced by using an appropriate high-K dielectric material in CNTFET as elucidated in [19].…”

Section: >>mentioning

confidence: 99%

Effect of Device Parameters on Carbon Nanotube Field Effect Transistor in Nanometer Regime

Sinha

Chaudhury

2015

JNanoR

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In this paper, we have analyzed the effect of chiral vector, temperature, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage a CNTFET provides over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector pair in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime.

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“…More detailed models, in particular those developed at the IEF-Orsay in the group of Ph. Dollfus and S. Retailleau, include the impact of phonon scattering and have improved to a point where they become valuable guides for the design of future high frequency devices [59,73,74].…”

Section: High Frequency Carbon Nanotube Transistorsmentioning

confidence: 99%

Carbon nanotube chemistry and assembly for electronic devices

Derycke

Auvray

Borghetti

et al. 2009

Comptes Rendus. Physique

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Carbon nanotubes (CNTs) have exceptional physical properties that make them one of the most promising building blocks for future nanotechnologies. They may in particular play an important role in the development of innovative electronic devices in the fields of flexible electronics, ultra-high sensitivity sensors, high frequency electronics, opto-electronics, energy sources and nanoelectromechanical systems (NEMS). Proofs of concept of several high performance devices already exist, usually at the single device level, but there remain many serious scientific issues to be solved before the viability of such routes can be evaluated. In particular, the main concern regards the controlled synthesis and positioning of nanotubes. In our opinion, truly innovative use of these nano-objects will come from: (i) the combination of some of their complementary physical properties, such as combining their electrical and mechanical properties; (ii) the combination of their properties with additional benefits coming from other molecules grafted on the nanotubes (this route being particularly relevant for gas-and bio-sensors, opto-electronic devices and energy sources); and (iii) the use of chemically-or bio-directed self-assembly processes to allow the efficient combination of several devices into functional arrays or circuits. In this article, we review our recent results concerning nanotube chemistry and assembly and their use to develop electronic devices. In particular, we present carbon nanotube field effect transistors and their chemical optimization, high frequency nanotube transistors, nanotube-based opto-electronic devices with memory capabilities and nanotube-based nano-electromechanical systems (NEMS). The impact of chemical functionalization on the electronic properties of CNTs is analyzed on the basis of theoretical calculations.

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Influence of capacitive effects on the dynamic of a CNTFET by Monte Carlo method

Cited by 11 publications

References 25 publications

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

Effect of Device Parameters on Carbon Nanotube Field Effect Transistor in Nanometer Regime

Carbon nanotube chemistry and assembly for electronic devices

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