Inefficiencies in the Cache Hierarchy

Laer, Anouk Van; Wang, William Yang; Emmons, Chris

doi:10.1145/2818950.2818980

Proceedings of the 2015 International Symposium on Memory Systems 2015

DOI: 10.1145/2818950.2818980

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Inefficiencies in the Cache Hierarchy

Anouk Van Laer

William Yang Wang

Chris Emmons

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2024

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An analysis of cache configuration’s impacts on the miss rate of big data applications using gem5

Dave,

Kotak

2024

Serb J Electr Eng

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This work aims to analyze the impacts of cache configurations on miss rates of big data benchmarks with varying level 1 instruction (L1I) and data (L1D) caches using the gem5 simulator. The cache miss rate of nine big data applications from four benchmark suits is analyzed with different cache configurations, such as increasing the cache size, varying the associativity, and altering the line size. The gem5 provides a versatile platform for conducting detailed experiments. The study sheds light on the relationship between cache and big data workloads, thus offering insights into optimizing cache configurations? effect on miss rates for improved performance.

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An analysis of cache configuration’s impacts on the miss rate of big data applications using gem5

Dave,

Kotak

2024

Serb J Electr Eng

View full text Add to dashboard Cite

show abstract

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Inefficiencies in the Cache Hierarchy

Cited by 1 publication

References 14 publications

An analysis of cache configuration’s impacts on the miss rate of big data applications using gem5

An analysis of cache configuration’s impacts on the miss rate of big data applications using gem5

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