2020
DOI: 10.1109/tpel.2019.2918174
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Inductor Saturation Compensation With Resistive Decoupling for Single-Phase Controlled VSC Systems

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Cited by 10 publications
(10 citation statements)
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“…When the current dc-bias is zero, the rise time is approximately 3-4 ms whereas when the d-axis current dc-bias level is 10 A, the rise time of the CSCC method is around 1 ms. This bandwidth shrinkage phenomenon in 3P3W VSCs with CSCC is similar to the case that of single-phase controlled VSCs under dc excitation [8], [23].…”
Section: B Dynamic Responsesupporting
confidence: 65%
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“…When the current dc-bias is zero, the rise time is approximately 3-4 ms whereas when the d-axis current dc-bias level is 10 A, the rise time of the CSCC method is around 1 ms. This bandwidth shrinkage phenomenon in 3P3W VSCs with CSCC is similar to the case that of single-phase controlled VSCs under dc excitation [8], [23].…”
Section: B Dynamic Responsesupporting
confidence: 65%
“…Considering the d-axis to d-axis and q-axis to q-axis magnitude plots in Fig. 5 (a) and (b) for θ = 0 and θ = π/3 under fullload operation, the d-axis bandwidth (ω BW −dd ) and q-axis bandwidth (ω BW −qq ) are observed to be much smaller than the design bandwidth ω BW which is called bandwidth shrinkage [8], [23] and elaborated in [7]. Moreover, the phase responses in Fig down to 62 degrees decreasing the robustness of the stability of the closed-loop current control system [22].…”
Section: A Command To Output Characteristicsmentioning
confidence: 99%
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“…Recent studies [14][15][16] showed that it was possible to design smaller and lighter SMPS by exploiting ferrite-core inductors operating in partial saturation. In this situation, the inductance drops as the inductor current increases, with a strong dependence on the core temperature (at higher temperatures, the inductance starts dropping for lower current values).…”
Section: Introductionmentioning
confidence: 99%