Inductor-less 10Gb/s CMOS Transimpedance Amplifier Using Source-follower Regulated Cascode and Double Three-order Active Feedback

Abstract

have been successfully implemented by using various In this work, a 10Gb/s CMOS transimpedance technologies such as SiGe, BiCMOS, GaAs, bipolor and amplifier using the source-follower regulated cascode and CMOS. double active feedback schemes is developed based on When considering the CMOS fabrication the TSMC 0. 18ptm CMOS technology. The proposed

A low-power and high-gain frontend for GHz application using trans-impedance amplifier for fast particle detection

“…Some of the latest works proposed the regulated cascode (RGC) topology as the core of a fast TIA ASIC chip [14,[21][22][23]. As shown in figure 1(a), the RGC topology exhibits a transimpedance gain that is approximately proportional to the resistive load at the output node, that is, 𝑍 𝑇 ,𝑅𝐺𝐶 ≈ 𝑅 2 .…”

A low‐power CMOS transimpedance amplifier in 90‐nm technology for 5‐Gbps optical communication applications

“…In the recent years, researchers have discussed and analyzed different circuit structures and techniques to improve the performance of the TIA circuits for using in high‐speed communication applications. These techniques are as follows: f T doubler, shunt peaking, inductive peaking and series peaking technique, active feedback, 3D inductor serial peaking, slew boosting, Regulated Cascode (RGC), common‐drain feedback, T‐coil inductor matching, negative impedance compensation, double three‐order active feedback, stagger tuning, Л‐network, voltage‐current feedback, the zero and pole cancellation, and a three‐dimensional inductor converter . In addition, structures that are usually used as TIA building blocks to alleviate the bandwidth reduction are as follows: RGC structure, stagger tuning, and T‐coil inductor matching.…”

“…Furthermore, forming a negative impedance as in Han et al requires a capacitance to be used. Also, in the technique of T‐coil inductor matching, in order to increase the gain and frequency bandwidth of the circuit, an inductor coupling is used which occupies a large area on the chip . Furthermore, extra power is consumed using f T doubler technique and slew boosting in comparison with RGC circuit structure to extend the bandwidth of a TIA…”