Inductance characterization of small interconnects using test-signal method

Shah, Jeet; Desai, Madhav P.; Sanyal, Subrata

doi:10.1109/icvd.2000.812636

VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design

DOI: 10.1109/icvd.2000.812636

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Inductance characterization of small interconnects using test-signal method

Jeet Shah

Madhav P. Desai²,

Subrata Sanyal³

Abstract: Abstract

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Energy Optimization for RC and RLC Interconnect Design in Low Power VLSI

Bhardwaj,

Jain,

Sohal

2024

MNS

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Background: The global RC interconnects have become the controlling parameter for a circuit’s performance. But with the decrease in technology, an increase in resistance has become prominent. This increase further directly affects the performance of the system by increasing the performance parameters of the circuit like delay and power consumption. To resolve this issue and to be compatible with Internet of Things (IoT) applications, the interconnect circuits are required to be high speed with less heat generation Methods: In this paper, a new RC and RLC interconnect circuit design was proposed for 45nm technology to enhance the performance parameters. Furthermore, the RC interconnect design was simulated for lumped and distributed networks. The parasitic component values (resistance, inductance, and capacitance) are evaluated using PTM technology. Results: The proposed interconnect circuit's resistance value decreased by a factor of 4, but the capacitance remains the same. Furthermore, power consumption and delay values were attained. An overall comparison was done between RC and RLC networks. Conclusion: 63.3% power improvement and 24.87% delay improvement were observed in the RLC network over RC distributed network.

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Energy Optimization for RC and RLC Interconnect Design in Low Power VLSI

Bhardwaj,

Jain,

Sohal

2024

MNS

View full text Add to dashboard Cite

show abstract

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Inductance characterization of small interconnects using test-signal method

Abstract: Abstract

Cited by 1 publication

References 7 publications

Energy Optimization for RC and RLC Interconnect Design in Low Power VLSI

Energy Optimization for RC and RLC Interconnect Design in Low Power VLSI

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