Incremental 2D Delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis

A Comprehensive Survey on Delaunay Triangulation: Applications, Algorithms, and Implementations Over CPUs, GPUs, and FPGAs

“…In [27], a 2D Delaunay triangulation core for surface reconstruction was implemented on a Field Programmable Gate Array (FPGA) chip using a high-level synthesis 9 . In particular, the FPGA implemented the Incremental Algorithm (see Algorithm 3).…”