Increasing the switching speed of high-voltage IGBTs

Robb, F.; Wan, I.; Yu., Shakarian

doi:10.1109/ispsd.1997.601486

Cited by 7 publications

(2 citation statements)

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“…There has been significant effort to reduce the power losses by reducing the current fall time [1]. In fact, the fall time is considered a good representation of the power losses in the device [2]. We believe that this presents an optimistic idea of the total turnoff losses because our simulations performed for the IGBT during inductive load turn off with different minority carrier Manuscript …”

Section: Introductionmentioning

confidence: 99%

Modeling the [dV/dt] of the IGBT during inductive turn off

Ramamurthy¹,

Sawant

Baliga

1999

IEEE Trans. Power Electron.

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Insulated gate bipolar transistor (IGBT)-based pulsewidth modulation (PWM) inverters are commonly used in inductive load circuits such as motor control. During clamped inductive load turn off of the IGBT, high-power losses occur during two phases. Due to the large inductive motor load, the voltage across the IGBT rises to the bus voltage while carrying the full-rated current. In the second phase, the current decreases as the IGBT goes into its forward blocking mode. In this paper, the turn-off process during the first phase is analyzed in detail for the first time. A simple analytical model has been derived, based upon the initial steady-state minority carrier distribution, which allows predicting the rate of rise of the voltage during this time period where the collector current remains constant. The predictions of the analytical model are in excellent agreement with results obtained from two-dimensional (2-D) numerical simulations over a broad range of minority carrier lifetime values. This analytical model provides a good estimate (within 10%) of the power losses incurred during the first phase of turn off.

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Section: Introductionmentioning

confidence: 99%

Modeling the [dV/dt] of the IGBT during inductive turn off

Ramamurthy¹,

Sawant

Baliga

1999

IEEE Trans. Power Electron.

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“…In particular, the He ion implantation technique [25], provides very thin ( 50 nm) low-lifetime regions and allows the design of user defined carrier lifetime profile [26]. A number of applications of local lifetime control technique are presented in [20], [22], and [27].…”

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confidence: 99%

Numerical analysis of local lifetime control for high-speed low-loss P-i-N diode design

Napoli

Strollo

Spirito

1999

IEEE Trans. Power Electron.

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The effect of localized lifetime control technique on the static and dynamic behavior of a power P-i-N diode is investigated in this paper. Mixed mode device circuit simulations are used in order to analyze the effect of the width and position of a reduced lifetime region on the diode. The simulations show that the optimal position for the low-lifetime region is at the beginning of the base region on the anode side, while the optimal width of the low-lifetime region depends on the amount of lifetime reduction. The local lifetime control design technique is shown to be effective in reducing the turn-off time and increasing diode softness with a little worsening of on-state voltage drop.It is shown that the tradeoff curve obtained by diodes using local lifetime control is better than the one achieved with lifetime killing in the whole epilayer region.Index Terms-Charge carrier lifetime, local lifetime control, P-i-N diodes, power semiconductor device.

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