Incorporation of tungsten or cobalt into TaN barrier layers controls morphology of deposited copper

Abstract

Progress in semiconductor devices, which has enabled the information and communications technology explosion of the 21st century, has been driven by Moore’s Law and the accompanying aggressive scaling of transistors. However, it is now acknowledged that the currently used copper interconnects are becoming a bottleneck in sub-nm scaling. Semiconductor devices require a diffusion barrier and a seed layer in the volume available to the interconnect metal. This then limits the minimum size of the interconnect and copper suffers from a preference to form 3D islands which are non-conducting rather than conducting films. Therefore there is a pressing need to either replace copper, which has its own difficulties, or to reduce the volume taken up by the diffusion barrier and liner; ideally finding a single material displaying both properties is needed. We have previously shown that incorporation of Ru into the surface layer of TaN is a strong alternative to the usual TaN/Ta or TaN/Ru stacks. In this work we study other possible metals that can be incorporated into TaN, namely Co and W, which are less expensive and critical than Ru and can potentially outperform it. Our first principles density functional theory (DFT) results from static relaxations and ab initio Molecular Dynamics (aiMD) show that there are several compositions of both Co- and W-doped TaN which should promote growth of 2D copper interconnects without compromising the barrier properties of TaN. With this selection of materials it should be possible to design new experimental processes that promote downscaled copper interconnects for the next generation of electronic devices. Additionally, our work presents an improved method towards prediction of thin film morphology on a given substrate, which can be of use for a variety of materials science applications.

Effect of Potassium Ferrocyanide on CMP Performance of Ruthenium in H2O2-based Slurries

“…As the pivotal innovations of integrated circuits over the past several decades, the application of copper(Cu) interconnects and low-k dielectric materials considerably facilitate the successive reduction of the technology nodes followed Moore's law. 1,2 These innovations, however, are along with a significant problem: copper diffusion. 3 Copper atoms easily diffuse into the dielectric layers and subsequently become the deep level acceptor impurities, thus forming a recombination center that lowers the lifetime of nonequilibrium carriers, and eventually making device performance degradation or even failure.…”

“…3 Copper atoms easily diffuse into the dielectric layers and subsequently become the deep level acceptor impurities, thus forming a recombination center that lowers the lifetime of nonequilibrium carriers, and eventually making device performance degradation or even failure. 2,4,5 It is for this reason that an effective diffusion barrier is deposited between the dielectric materials and copper interconnects to thoroughly separate them. 5,6 The way of accomplishing this on integrated circuit with feature size above 32 nm is to apply a combination of tantalum(Ta) and tantalum nitride (TaN) as barrier layer for multilayer copper interconnect.…”