Incorporating Backchannel Training into Signal Integrity SerDes Compliance

Choe, David; Willis, Ken

doi:10.1109/emcsi.2018.8495190

Cited by 1 publication

(2 citation statements)

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“…13 In recent years, link training adaptation techniques have been incorporated into various wireline standards such as Infiniband, Fibre Channel, and PCI Express Gen 3 and 4. 14 In a link training or back channel training environment, the transmitter and receiver can communicate through the back channel adaptation. It automatically tunes the transmitter and receiver settings to optimize the SI and bit error rate (BER).…”

Section: Introductionmentioning

confidence: 99%

“…Hence, automatically optimized settings are required at both ends of the interconnect, where hybrids are deployed to adapt to different channel lengths and environmental conditions at different data rates 13 . In recent years, link training adaptation techniques have been incorporated into various wireline standards such as Infiniband, Fibre Channel, and PCI Express Gen 3 and 4 14 . In a link training or back channel training environment, the transmitter and receiver can communicate through the back channel adaptation.…”

Section: Introductionmentioning

confidence: 99%

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An adaptive link training based hybrid circuit topology for full‐duplex on‐chip interconnects

Govindaswamy

Kammari

Pasupureddi

2023

Circuit Theory & Apps

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SummaryThis work proposes a link training based half‐rate dynamic current‐steering echo‐cancellation hybrid circuit topology for full‐duplex signaling that performs echo cancellation by deploying a bit error detection unit and backchannel adaptation. In addition, this work proposes a power‐efficient half‐rate dynamic current‐steering logic hybrid circuit for full‐duplex signaling over on‐chip interconnects for simultaneous transmission and reception. The half‐rate dynamic current‐steering hybrid circuit topology has low static power consumption compared with traditional current‐mode circuit topology implementations, thanks to the discrete nature of the current‐steering hybrid topology. The proposed scheme is implemented in 1.2 V, 65‐nm complementary metal‐oxide semiconductor (CMOS). The performance results show that the link training scheme sets the control bits for both the transmitter driver and hybrid circuit topology when the backchannel adaptation loop gets locked for 1‐ and 3‐mm interconnects for process, voltage, and temperature (PVT) variations. The proposed hybrid circuit topology is able to receive the required far‐end transmitted data with the link training scheme and has the differential recovered received signal voltage swing of 1.2 V for both 1‐ and 3‐mm interconnect at the 10‐Gb/s data rate. The total power consumption of the hybrid is 3 and 3.5 mW for 1‐ and 3‐mm interconnect with an energy efficiency of 0.6 and 0.7 pJ/bit, respectively, at 10‐Gb/s full‐duplex operation.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%