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Abstract

Nanocomputing using nanowire tiles Physical limitations may impede further miniaturization of microelectronics using current lithographically fabricated silicon transistor designs. To develop a nanocomputer architecture that transcends such physical limitations, Jun Yao et al. (pp. 2431-2435) synthesized nanowires with diameters less than 20 nm and implemented an assembly technique to organize the nanowires into six highly ordered nanowire crossbar arrays. The nanowire transistor arrays shared the same crossbar structure and were configured as three logic tiles programmed for distinct logic functions. Tile 1 was programmed to perform simple arithmetic functions, and tiles 2 and 3 were programmed to register the results from tile 1. The approach provided a manufacturing advantage, compared to conventional circuit designs that require different layouts for different logic functions. By interconnecting the three logic tiles with 180 transistors, the authors constructed a finite-state machine that was able to compute, register, and update the internal logic state of the self-contained nanochip according to external stimuli. The study suggests that powerful and general nanocomputing capability may be possible by interconnecting additional nanowire logic tiles, and that further miniaturization of electronics may be feasible using such nanoprocessors, according to the authors.-P.G.