In-Memory Intelligence

Finkbeiner, Tim; Hush, Glen; Troy, Larsen,; Lea, Perry; Leidel, John D.; Manning, Troy D.

doi:10.1109/mm.2017.3211117

Cited by 19 publications

(5 citation statements)

References 9 publications

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“…Various PIM proposals exploit vast memory subarray parallelism and perform analog computing directly in the sense amplifiers. Micron's In-Memory Intelligence (IMI) is a standard DRAM in form and function with the ability for vector instructions over the entire bank [28]. IMI is capable of XOR and AND operation at sense amplifier lever.…”

Section: Related Workmentioning

confidence: 99%

On Key–Value Sort With Active Compute Memory

Esmaili-Dokht,

Guiot,

Radojković

et al. 2024

IEEE Trans. Comput.

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We propose the Active Compute Memory (ACM), a near-memory-processing architecture capable of performing key-value sort directly in the DRAM. In the ACM architecture, sort is merely the writing of data into memory with one addressing protocol (perspective) and reading it back with different perspective. The first perspective is conventional, based on the data address; the second perspective is the sorted order. The ACM requires additional tables to store the meta-data and moderate control logic enhancements that can be implemented directly in the DRAM silicon. By these modest enhancements to DRAM, ACM exploits the parallelism inherently available in the row buffer to enable sort with O(n) complexity. This leads to an order of magnitude improvement in ACM performance and energy compared to conventional O(n log n) CPU-centric sort algorithms. The ACM also shows superior performance compared to other near-memory sort accelerators. This is because the ACM processing is done near the row buffer and it exploits much lower memory access latency, higher bandwidth and wider parallel processing. The sort operation covered in this paper is just an example of an address management operation that can be efficiently implemented directly in the DRAM silicon. We release as an open source the simulation infrastructure for the ACM performance and energy modeling. We would encourage the community to use it, adapt it to other PIM proposals, and share their own evaluations.

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Section: Related Workmentioning

confidence: 99%

On Key–Value Sort With Active Compute Memory

Esmaili-Dokht,

Guiot,

Radojković

et al. 2024

IEEE Trans. Comput.

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“…A medium number of architectures have been proposed in this class: Resistive Associative Processor (ReAP) [137], A Processing-in-Memory Architecture for Neural Network Computation in ReRAM-based Main Memory (PRIME) [21], A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic (ISAAC) [111], In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (Ambit) [110], A Processing-in-Memory Architecture for Bulk Bitwise Operations (Pinatubo) [80], In-Memory Intelligence (IMI) [32], Compute Caches (Compute$) [1],…”

Section: Computation-in-memory -Periphery (Cim-p)mentioning

confidence: 99%

A Classification of Memory-Centric Computing

Nguyen

Lebdeh

et al. 2020

J. Emerg. Technol. Comput. Syst.

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Technological and architectural improvements have been constantly required to sustain the demand of faster and cheaper computers. However, CMOS down-scaling is suffering from three technology walls: leakage wall, reliability wall, and cost wall. On top of that, a performance increase due to architectural improvements is also gradually saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall. Hence, a lot of research is focusing on proposing and developing new technologies and architectures. In this article, we present a comprehensive classification of memory-centric computing architectures; it is based on three metrics: computation location, level of parallelism, and used memory technology. The classification not only provides an overview of existing architectures with their pros and cons but also unifies the terminology that uniquely identifies these architectures and highlights the potential future architectures that can be further explored. Hence, it sets up a direction for future research in the field.

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“…Some proposed architectures return to the older processor-inmemory (PIM) and "intelligent RAM" [57] ideas. Simulations of architectures focusing on near-data processing [33] including in-memory [32] and near-memory [31] show great promise for increasing performance while also drastically reducing energy usage.…”

Section: Related Workmentioning

confidence: 99%

Programming Strategies for Irregular Algorithms on the Emu Chick

Hein¹,

Eswar²,

Yaşar³

et al. 2019

Preprint

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The Emu Chick prototype implements migratory memory-side processing in a novel hardware system. Rather than transferring large amounts of data across the system interconnect, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each remote memory read. Previous work has characterized the performance of the Chick prototype in terms of memory bandwidth and programming differences from more typical, non-migratory platforms, but there has not yet been an analysis of algorithms on this system. This work evaluates irregular algorithms that could benefit from the lightweight, memory-side processing of the Chick and demonstrates techniques and optimization strategies for achieving performance in sparse matrix-vector multiply operation (SpMV), breadth-first search (BFS), and graph alignment across up to eight distributed nodes encompassing 64 nodelets in the Chick system. We also define and justify relative metrics to compare prototype FPGA-based hardware with established ASIC architectures. The Chick currently supports up to 68x scaling for graph alignment, 80 MTEPS for BFS on balanced graphs, and 50% of measured STREAM bandwidth for SpMV.

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In-Memory Intelligence

Cited by 19 publications

References 9 publications

On Key–Value Sort With Active Compute Memory

On Key–Value Sort With Active Compute Memory

A Classification of Memory-Centric Computing

Programming Strategies for Irregular Algorithms on the Emu Chick

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