DOI: 10.32657/10356/146888
|View full text |Cite
|
Sign up to set email alerts
|

In-memory analytical query processing on GPUs

Abstract: The high global memory bandwidth and the large number of parallel cores available in modern Graphics Processing Units (GPUs) make them ideal for highperformance Online Analytical Processing (OLAP) systems. However, it is challenging to design efficient high-performance query processing systems for GPUs due to the following reasons: 1) the rapid evolution of GPU hardware in the last decade, 2) the significant differences in the hardware architecture of GPUs when compared to CPUs, 3) the high overhead of moving … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
0
0

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
(1 citation statement)
references
References 130 publications
0
0
0
Order By: Relevance
“…Processing-in-Memory (PiM) is a promising paradigm that augments a system's memory with compute capability [1][2][3][4][5] to alleviate the data movement bottleneck between processing and memory units [2,[6][7][8][9][10][11][12][13][14][15][16][17]. PiM architectures can be classified into two categories [1,18]: 1) Processing-near-Memory (PnM), where computation takes place in dedicated processing elements (e.g., accelerators [11,, processing cores [11, 30-32, 41, 44-58], reconfigurable logic [59][60][61][62][63]) placed near the memory array (e.g., [11,), and 2) Processingusing-Memory (PuM), where computation takes place inside the memory array by exploiting intrinsic analog operational properties of the memory device (e.g., [41,55,).…”
Section: Introductionmentioning
confidence: 99%
“…Processing-in-Memory (PiM) is a promising paradigm that augments a system's memory with compute capability [1][2][3][4][5] to alleviate the data movement bottleneck between processing and memory units [2,[6][7][8][9][10][11][12][13][14][15][16][17]. PiM architectures can be classified into two categories [1,18]: 1) Processing-near-Memory (PnM), where computation takes place in dedicated processing elements (e.g., accelerators [11,, processing cores [11, 30-32, 41, 44-58], reconfigurable logic [59][60][61][62][63]) placed near the memory array (e.g., [11,), and 2) Processingusing-Memory (PuM), where computation takes place inside the memory array by exploiting intrinsic analog operational properties of the memory device (e.g., [41,55,).…”
Section: Introductionmentioning
confidence: 99%