In-die overlay metrology method using SEM images

Harada, Masaru; Minekawa, Yohei; Fukunaga, Fumihiko; Nakamae, Koji

doi:10.1117/1.jmm.17.4.044004

Cited by 4 publications

(5 citation statements)

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“…However, in BSE images, the signal from the lower layer pattern is often weak or undetected, and the pattern edge is blurred due to the diffusion of the incident beam in the upper layer. As the result, the precision and accuracy of pattern contour extraction and the sensitivity of pattern measurement are reduced [6,7,8]. This is difficulty in pattern contour extraction and overlay measurement.…”

Section: Feature and Difficulty In Measuring Bse Imagementioning

confidence: 99%

Utilization of active contour model with 3D-SEM simulation for see-through BSE image of high voltage SEM

Oya,

Okamoto,

Nakazawa

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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As semiconductor device structures continue to shrink and increase its complexity, the need for precise measurement techniques extends beyond single-layer patterning to encompass overlay and Edge Placement Error (EPE) across multiple layers. Traditionally, overlay and EPE have been managed using dedicated patterns and equipment, respectively. However, as manufacturing processes become more intricate, there arises a necessity to measure these parameters directly on actual device patterns. Addressing this demand, High Voltage-Scanning Electron Microscopy (HV-SEM) emerges as a viable tool for on-device-overlay measurement. Nevertheless, challenges persist in achieving accurate measurements using seethrough Backscattered Electron (BSE) imaging due to low contrast and sharpness resulting from electron diffusion through upper-layer patterns. This impedes precise contour extraction and reduces pattern measurement sensitivity. Moreover, in layouts where pattern contours between layers are closely spaced, precise contour extraction becomes even more challenging. To address these issues, a specialized contour extraction function is essential for achieving precise and stable pattern extraction from BSE images. In this paper, we propose a novel HV-SEM overlay measurement methodology utilizing active contour model with Electron Beam (EB) simulation. Synthetic images, designed to emulate the latest device structures and based on BSE features obtained through EB simulation, were employed for evaluation. The results demonstrate the method's robustness to noise and its ability to accurately extract the contours of partially hidden lowerlayer patterns. The proposed approach will enhance the accuracy of HV-SEM overlay measurements, thereby expanding the utility of HV-SEM see-through BSE imaging in semiconductor manufacturing processes.

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Section: Feature and Difficulty In Measuring Bse Imagementioning

confidence: 99%

Utilization of active contour model with 3D-SEM simulation for see-through BSE image of high voltage SEM

Oya,

Okamoto,

Nakazawa

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

View full text Add to dashboard Cite

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“…53,54 The placement error of the current patterns (dX c ; dY c ) and the placement error of the reference patterns (dX r ; dY r ) are calculated using a template matching method. 55 Based on the technique, the placement error of the segmented pattern is obtained as a difference between the two images. This developed matching method extracts the position of each pattern contained in two images.…”

Section: Overlay Using Comparison With Reference Imagementioning

confidence: 99%

“…Harada has shown the proposed method has linearity and sensitivity for the subpixel order overlay in the numerical experiments even if the patterns have size variations. 55 6 SEM-OL Metrology for Buried Patterns…”

Section: Overlay Using Comparison With Reference Imagementioning

confidence: 99%

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Ito

Hasumi

2019

J. Micro/Nanolith. MEMS MOEMS

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Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.

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“…The overlay of actual circuit patterns therefore needs to be measured by using a critical dimension scanning electron microscope (CD-SEM) [1,2]. In cases where the actual circuit patterns of a measurement target consist of upper layer patterns and buried lower layer patterns, an overlay measurement method using both secondary electrons (SE) images and backscattered electrons (BSE) images obtained from a high voltage CD-SEM (HV-SEM) has been proposed [3]. It was demonstrated that in cases where the upper patterns and buried lower patterns are fabricated using different materials, buried lower layer patterns appear with their material contrast in the BSE image [3].…”

Section: Introductionmentioning

confidence: 99%

“…Since the pattern matching technique uses two-dimensional signal information, it has better measurement accuracy for low signal-to-noise ratio (S/N) patterns compared to the edge detection technique that uses one-dimensional signal information. A method has also been proposed that measures the lower layer patterns by applying pattern matching between the target image and a template image in which the regions of the upper layer patterns are masked [3]. This method does not require the placing of measurement area cursors.…”

Section: Introductionmentioning

confidence: 99%

A method for dynamic placement of overlay measurement area cursors using segmentation technique

Kyogoku,

Harada,

Osaki

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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As the design rules for semiconductor devices continue to shrink, layer-to-layer overlay of actual circuit patterns needs to be measured by using a critical dimension scanning electron microscope (CD-SEM). In addition to the overlay, process variations are making not only local size variations but also local position errors in patterns on the same layer increasingly non-negligible compared to pattern size. In cases where upper and lower patterns partially overlap, these variations and errors cause variations to occur in the positions and visible area of the lower layer patterns in SEM images. As a result, the center position of each lower layer pattern has become difficult to accurately measure resulting in errors in the overlay measurement. In response to this problem, we have developed a method for dynamically placing measurement area cursors for overlay metrology using segmentation technique. This method determines a measurement area cursor by recognizing the position and size of each lower layer pattern through segmentation images generated from the target SEM images using unsupervised deep learning. The performance of this method is evaluated by creating imitated images having the programmed overlay, the local size variations, and the local position errors. We compared the measurement results for the imitated images obtained by the proposed method and a conventional method that uses fixed measurement area cursors and found that the proposed method maintains sensitivity and repeatability even for targets where sensitivity and repeatability degrade with the conventional method due to process variations.

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In-die overlay metrology method using SEM images

Cited by 4 publications

References 0 publications

Utilization of active contour model with 3D-SEM simulation for see-through BSE image of high voltage SEM

Utilization of active contour model with 3D-SEM simulation for see-through BSE image of high voltage SEM

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

A method for dynamic placement of overlay measurement area cursors using segmentation technique

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