Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis

Tendolkar, N.; Belete, D.; Schwarz, Bill; Podnar, Bob; Gupta, Akshay; Karako, Steve; Cheng, Wu-Tung; Babin, Alex; Tsai, Kun-Han; Tamarapalli, Nagesh; Aldrich, G.

doi:10.1109/test.2006.297623

Cited by 16 publications

(3 citation statements)

References 20 publications

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“…For patterns with both at-speed and slow speed cycles, we assume that the slow speed cycles don't activate any failure; they only propagate failures captured at the atspeed cycle. If there is a slow speed cycle after the at-speed cycles, the scan cells that capture at-speed failures need to be identified [11] before applying the proposed speed path debug for the at-speed cycles.…”

Section: Discussionmentioning

confidence: 99%

“…People have been using at-speed scan test patterns to identify delay defects during product silicon debug [11][12][13][14][15][16][17][18][19][20][21][22]. Path delay fault model has been used in previous works to diagnose delay defects [12] [13] [14] [15], but the diagnostic resolution for path delay faults hasn't achieved an acceptable level, especially when there are multiple faults in the circuit under diagnosis.…”

Section: Review Of Previous Workmentioning

confidence: 99%

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Speed-Path Debug Using At-Speed Scan Test Patterns

Guo

Cheng

Tsai

2009

2009 14th IEEE European Test Symposium

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Speed path debug is a critical step to improve the performance of high performance VLSI designs. The purpose of speed path debug is to identify the performance limiting paths and fix them in the next product stepping so that the chip can run at a higher clock frequency. This paper investigates speed path debug techniques using atspeed scan test patterns. For each failing scan cell, the failing paths are identified based on structural analysis of logic simulation values. We further propose two metrics to rank the identified speed paths based on logic value analysis and based on timing information calculated for the failing pattern. Experimental results show the effectiveness of the proposed speed path debug technique.

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Section: Discussionmentioning

confidence: 99%

Section: Review Of Previous Workmentioning

confidence: 99%

Speed-Path Debug Using At-Speed Scan Test Patterns

Guo

Cheng

Tsai

2009

2009 14th IEEE European Test Symposium

Self Cite

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show abstract

“…Logic simulation and enhanced critical path tracing is used in [14], but it may be computationally expensive to find all possible multiple sensitized paths. The solution presented in [12] [13] uses fault simulation rather than critical path tracing and takes advantage of the SLAT concept [24] for multiple defects. To improve diagnosis resolution, timing information is used in [8][10] [11] [15].…”

Section: Introductionmentioning

confidence: 99%

Diagnostic test generation for small delay defect diagnosis

Guo

Cheng

Kobayashi

et al. 2010

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test

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Small delay defect is becoming an important defect mechanism that leads to yield loss and performance hit in high performance VLSI designs. Small delay defects usually cause a small number of failures in production test patterns, and hence provide little evidence for logic fault diagnosis to isolate a defect. In this paper, we present a diagnostic test generation technique that targets creating more tester failures for a small delay defect in order to improve the diagnostic resolution. Experimental results show the effectiveness of the proposed technique. 978-1-4244-5271-2/10/$26.00 ©2010 IEEE

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Conventional Methods for Fault Diagnosis

Raman

2023

Machine Learning Support for Fault Diagnosis of System-on-Chip

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Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis

Cited by 16 publications

References 20 publications

Speed-Path Debug Using At-Speed Scan Test Patterns

Speed-Path Debug Using At-Speed Scan Test Patterns

Diagnostic test generation for small delay defect diagnosis

Conventional Methods for Fault Diagnosis

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