Improving the test quality for scan-based BIST using a general test application scheme

Tsai, Huan-Chih; Cheng, Kwang-Ting; Bhawmik, S.

doi:10.1109/dac.1999.782113

Cited by 3 publications

(1 citation statement)

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“…Multi-cycle test that applies more than one capture clock to the circuit is proposed to test volume reduction by allowing multiple tests at each test pattern (scan-in pattern) [8]- [11]. In multi-cycle test, for each test pattern (scan-in pattern generated by an on-chip Random Pattern Generator such as a Liner Feedback Shift Register-LFSR), the test response captured at each capture cycle will be reused as test stimuli at the next capture cycles.…”

Section: ) the Low Power Consumptionmentioning

confidence: 99%

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

Al-Awadhi

Aono

Wang

et al. 2020

IEICE Trans. Inf. & Syst.

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Multi-cycle Test looks promising a way to reduce the test application time of POST (Power-on Self-Test) for achieving a targeted high fault coverage specified by ISO26262 for testing automotive devices. In this paper, we first analyze the mechanism of Stuck-at Fault Detection Degradation problem in multi-cycle test. Based on the result of our analysis we propose a novel solution named FF-Control Point Insertion technique (FF-CPI) to achieve the reduction of scan-in patterns by multi-cycle test. The FF-CPI technique modifies the captured values of scan Flip-Flops (FFs) during capture operation by directly reversing the value of partial FFs or loading random vectors. The FF-CPI technique enhances the number of detectable stuck-at faults under the capture patterns. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of FF-CPI technique in scan-in pattern reduction for POST.

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Section: ) the Low Power Consumptionmentioning

confidence: 99%