Improving the result of high-level synthesis using interactive transformational design

Larsson, Mats

doi:10.1007/bfb0105412

Cited by 4 publications

(2 citation statements)

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“…Veritas 40) is a theorem prover based on an extension of typed higher order logic, which provides an interactive environment for converting the specification into an implementation. Larsson 55) presented a transformational approach to digital system design based on the HOL proof system 36) . Hash 26) is another system based on the theorem prover HOL 36) .…”

Section: Transformational Synthesis Toolsmentioning

confidence: 99%

High-Level Verification

Kundu

Lerner

Gupta

2009

IPSJ Transactions on System LSI Design Methodology

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The growth in size and heterogeneity of System-on-Chip (SOC) design makes their design process from initial specification to IC implementation complex. System-level design methods seek to combat this complexity by shifting increasing design burden to high-level languages such as SystemC and SystemVerilog. Such languages not only make a design easier to describe using high-level abstractions, but also provide a path for systematic implementation through refinement and elaboration of such descriptions. In principle, this can enable a greater exploration of design alternatives and thus better design optimization than possible using lower level design methods. To achieve these goals, however, verification capabilities that seek to validate designs at higher levels as well their equivalences with lower level implementations are crucially needed. To the extent possible given the large space of design alternatives, such validation must be formal to ensure the design and important properties are provably correct against various implementation choices. In this paper, we present a survey of high-level verification techniques that are used for both verification and validation of high-level designs, that is, designs modeled using high-level programming languages. These techniques include those based on model checking, theorem proving and approaches that integrate a combination of the above methods. The high-level verification approaches address verification of properties as well as equivalence checking with refined implementations. We also focus on techniques that use information from the synthesis process for improved validation. Finally, we conclude with a discussion and future research directions in this area.

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Section: Transformational Synthesis Toolsmentioning

confidence: 99%

High-Level Verification

Kundu

Lerner

Gupta

2009

IPSJ Transactions on System LSI Design Methodology

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“…Also, they often cover only parts of the synthesis process, e. g. , the scheduling [12]. Furthermore, they are often not suitable for automation, but require the synthesis process to be guided interactively by the designer [9] and, thus, need the designer to be well grounded in formal methods.…”

Section: Introductionmentioning

confidence: 99%

Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis

Kapp

Sabelfeld

2004

Proceedings of the 41st Annual Design Automation Conference

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Formal synthesis ensures the correctness of hardware synthesis by automatically deriving the circuit implementation by behavior preserving transformations within a theorem prover.In this paper, we present a new approach to formal synthesis that is able to handle control flow intensive descriptions. In particular, we consider here the scheduling phase, which is a central task in high-level synthesis. We describe a methodology employing a new control flow oriented representation which allows the fully automatic scheduling of control flow intensive descriptions in formal synthesis. To obtain scheduled circuits of high quality, the scheduling is guided by conventional scheduling algorithms.

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