Improving the Quality of Delay-Based PUFs via Optical Proximity Correction

Forte, Domenic; Srivastava, Ankur

doi:10.1109/tcad.2013.2274940

Cited by 2 publications

(1 citation statement)

References 29 publications

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“…At layout and masking levels, causing fabrication variations requires the layout and masking engineer to act exactly in the opposite direction against any variation-limiting approaches. For example, PUF masks are better with PUF-aware OPC applied to improve their uniqueness [98], [99]. This approach can be applied wherever a variation is required in a portion of the circuit, whereas a regular OPC can normally be applied elsewhere.…”

Section: H Applicable Variation Enhancementsmentioning

confidence: 99%

Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Kamal

Mureşan

2019

IEEE Access

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An electronic physically unclonable function usually includes an on-chip error-correcting code unit, which is vulnerable to security attacks and adds area, power, and data processing time overheads. This paper proposes a mixed-signal physically unclonable function circuit for authentication purposes, which we call the enhanced capacitive physically unclonable function. It divides the input challenge word over multiple computational groups to decrease processing time, increase security, and eliminate the need for error-correcting code units. Most of the challenge bits control capacitive networks grouped into several capacitive cells, while some are analogized through two digital-to-analog converters. One digital-to-analog converter controls the discharge loads of the capacitive cells; the other controls the reference voltage of comparator units. Each comparator controls a counter that digitizes the discharge time into a response chunk. Most of these counters operate at high frequencies for more precise time-to-digital conversion and are overflown to act as roulettes to promote unpredictability. One counter is not overflown to generate a reference response chunk to support error handling. The design allows for more intrinsic variations throughout the fabrication process, leading to unique response chunks. It applies an expanding challenge-response pair approach, generating a 128-bit response word for a 64-bit challenge word. The capacitive nature of the design supports various security features. Simulating the circuit using 45 nm complementary metal-oxide semiconductor technology resulted in an average power of 921.67 µW, a layout area of 22,470 µm 2 , and an average data processing time of 118 µs.

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Section: H Applicable Variation Enhancementsmentioning

confidence: 99%

Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Kamal

Mureşan

2019

IEEE Access

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Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA)

Asha

Hsu

Patyal

et al. 2021

J. Emerg. Technol. Comput. Syst.

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Ring Oscillator Physical Unclonable Functions (RO-PUFs) exploit the inherent manufacturing process variations, such as systematic and stochastic variations, to generate secret PUF responses that are unique to the device. Stochastic variations are random, while systematic variation exhibits a strong spatial correlation. Therefore, systematic process variation reduces the randomness of the PUF response. This lowers the ability of a PUF response to uniquely identify and authenticate individual devices. Further, the impact of systematic variation is paramount when the two ROs in comparison are placed far apart. Comparing the ROs that are close to each other does improve the randomness, but the responses generated are unreliable and limiting the possible Challenge-Response Pairs (CRPs). In this article, we are proposing a method to reduce the impact of systematic process variation on the RO oscillation frequencies by using Principal Component Analysis (PCA). Principal Components (PCs) model the directions of systematic and stochastic variation present on a device. By projecting the oscillation frequencies in the direction of stochastic variation, the impact of systematic variation can be reduced. Our proposed method neither restricts the placement of ROs to close groups nor limits the possible CRPs. The method is evaluated on a large population of 218 Xilinx Artix-7 FPGAs. To evaluate the efficiency of the proposed method, we purposely paired the ROs that are placed far apart on the FPGA fabric. Results obtained prove the ability of the proposed method in removing the impact of systematic variation on the oscillation frequencies and thereby producing truly random responses.

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Improving the Quality of Delay-Based PUFs via Optical Proximity Correction

Cited by 2 publications

References 29 publications

Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA)

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