2012
DOI: 10.1007/978-3-642-30598-6_13
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Improving the Performance of Execution Time Control by Using a Hardware Time Management Unit

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Cited by 4 publications
(5 citation statements)
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“…Test results are given for the implementation with and without the TMU [6,7], to show the interrupt handler overhead caused by implementing execution time control for interrupts as seen in Figure 1. Testing of the TMU was done by simulation as it has not yet been included in a produced UC3 chip.…”
Section: Test Resultsmentioning
confidence: 99%
See 3 more Smart Citations
“…Test results are given for the implementation with and without the TMU [6,7], to show the interrupt handler overhead caused by implementing execution time control for interrupts as seen in Figure 1. Testing of the TMU was done by simulation as it has not yet been included in a produced UC3 chip.…”
Section: Test Resultsmentioning
confidence: 99%
“…Two implementations of execution time control exists for GNATforAVR32: a standard implementation using the COUNT / COMPARE registers of the AVR32 [6], and a hardware accelerated implementation using the Time Management Unit (TMU) [7]. The two implementations share the base design, and only differ in the low-level code interfacing to the hardware timers.…”
Section: Implementation On Gnatforavr32mentioning
confidence: 99%
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“…The implementation cost and run-time overhead of timers is moderate, and can be further reduced by using specialized hardware timers [11]. The feature has already been included in otherwise Ravenscar compliant run-time environments [5,10,13].…”
Section: Timersmentioning
confidence: 99%