Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering

Bousari, Nazanin Baghban; Anvarifard, Mohammad K.; Haji-Nasiri, Saeed

doi:10.1016/j.aeue.2019.06.017

Cited by 63 publications

(21 citation statements)

References 27 publications

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“…Results suggest that DHGO FinFET has improved I ON /I OFF ratio and low leakage current compared to other structures. 14 The RF noise performance of FinFET is reported for the variation in channel length, fin width, and number of fins. 15 They achieved a gain of 13.5 dB with noise figure of 1.35 dB at frequency of 10 GHz.…”

Section: Introductionmentioning

confidence: 99%

Study on impact of ferroelectric layer thickness on RF /analog and linearity parameters in ferroelectric‐FinFET

Saha

Bhowmick

Baishya

2021

Int J RF Mic Comp-Aid Eng

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In this paper, we systematically investigated the effect of ferroelectric (FE) layer thickness (t FE ) on transfer and RF/analog characteristics such as transconductance (g m ), total gate capacitance (C gg ), cut off frequency (f t ), transconductance frequency product, and unilateral power gain in Ferroelectric-FinFET (Fe-FinFET) through 3D TCAD simulator. Further, we highlighted the influence of t FE on linearity figure of merits (FoMs), higher order harmonics (g m2 and g m3 ), voltage intercept points (VIP 2 and VIP 3 ), third order power intercept point (IIP 3 ), third order intermodulation distortion (IMD 3 ), and 1-dB compression point (1-dB comp. Pnt.) for Fe-FinFET. Moreover, the harmonic distortion (HD) parameters like second and third order harmonic distortion (HD2 and HD3) and total harmonic distortion (THD) are reported taking t FE as a parameter. The noise spectral densities of Fe-FinFET taking t FE as parameter is also highlighted. The scaling of t FE has a significant impact on RF/analog parameters and these RF/analog FoMs are a function of t FE . It is also perceived that linearity and HD parameters are dependent on scaling of t FE . Results reveal that with increase in t FE , RF/analog characteristics degrades, whereas, superior linearity FoMs is achieved. It is also seen that HD parameters are improved with increased in t FE value. The increased in t FE leads to increase in noise spectral densities. Finally, the comparative study of electrical parameters of this work with the existing literature is investigated.

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Section: Introductionmentioning

confidence: 99%

Study on impact of ferroelectric layer thickness on RF /analog and linearity parameters in ferroelectric‐FinFET

Saha

Bhowmick

Baishya

2021

Int J RF Mic Comp-Aid Eng

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“…The gate leakage current is a critical factor that directly impacts performance characteristics [ 11 ]. As shown in [ 12 ], efforts to suppress leakage current even in the latest transistor structures have been continuously studied. TiN engineering (e.g., by controlling the thickness of TiN) was carried out to suppress the gate leakage current.…”

Section: Introductionmentioning

confidence: 99%

Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-K/Metal-Gate Device

2021

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In this study, a gate-stack engineering technique is proposed as a means of improving the performance of a 28 nm low-power (LP) high-k/metal-gate (HK/MG) device. In detail, it was experimentally verified that HfSiO thin films can replace HfSiON congeners, where the latter are known to have a good thermal budget and/or electrical characteristics, to boost the device performance under a limited thermal budget. TiN engineering for the gate-stack in the 28 nm LP HK/MG device was used to suppress the gate leakage current. Using the proposed fabrication method, the on/off current ratio (Ion/Ioff) was improved for a given target Ion, and the gate leakage current was appropriately suppressed. Comparing the process-of-record device against the 28 nm LP HK/MG device, the thickness of the electrical oxide layer in the new device was reduced by 3.1% in the case of n-type field effect transistors and by 10% for p-type field effect transistors. In addition, the reliability (e.g., bias temperature instability, hot carrier injury, and time-dependent dielectric breakdown) of the new device was evaluated, and it was observed that there was no conspicuous risk. Therefore, the HfSiO film can afford reliable performance enhancement when employed in the 28 nm LP HK/MG device with a limited thermal budget.

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“…Other techniques for low-voltage circuit design include the design of low-voltage technological devices. Different device structures have been proposed for low-power and low supply voltage applications [3][4][5][6][7]. Among these, steep-slope devices have been identified as a promising candidate.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of circuit performance of T‐shaped tunnel FET

Dubey

Kaushik

2020

IET Circuits, Devices & Systems

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This study investigates the analogue performance of a III-V tunnelling field-effect transistor (TFET). To explore the circuit performance of the TFET, a T-shaped TFET (TTFET) structure is investigated and its performance parameters are compared with a 14 nm simulation program with integrated circuit emphasis (SPICE)-based predictive technology model FinFET. The advantages and limitations of TTFET technology over its FinFET counterparts are discussed in detail by implementing the inverter, current mirror, track-and-hold (T/H), and differential amplifier circuits. It is observed that the TTFET inverter offers 1.56× higher maximum gain, 14.46× lower delay, and 12.13× lower-energy-delay product when compared with FinFET inverter in Fan-Out1 (FO1) configuration at V DD = 0.3 V. The TTFET-based current mirror and T/H circuit perform superior to their FinFET counterparts in terms of accuracy and delay. The TTFET-based differential amplifier provides 24.63 dB higher differential gain and 21.5 dB higher common-mode rejection ratio when compared with FinFET amplifier. Finally, the impact of the variation in process parameters on the device and circuit performance has been investigated. The standard deviation of 20% in oxide thickness, 20% in channel thickness, 20% in source doping, and 2% in metal work function results in a standard deviation 2.56% in delay of FO1 inverter from its nominal value.

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Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering

Cited by 63 publications

References 27 publications

Study on impact of ferroelectric layer thickness on RF /analog and linearity parameters in ferroelectric‐FinFET

Study on impact of ferroelectric layer thickness on RF /analog and linearity parameters in ferroelectric‐FinFET

Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-K/Metal-Gate Device

Evaluation of circuit performance of T‐shaped tunnel FET

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