Improving the accuracy and robustness of RRAM-based in-memory computing against RRAM hardware noise and adversarial attacks

Cherupally, Sai Kiran; Meng, Jian; Rakin, Adnan Siraj; Yin, Shihui; Yeo, Injune; Yu, Shimeng; Fan, Deliang; Seo, Jae-sun

doi:10.1088/1361-6641/ac461f

Cited by 6 publications

(4 citation statements)

References 30 publications

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“…IMC architectures are known for their improved energy efficiency and throughput, but they have some drawbacks. One such drawback is the limited precision of the IMC crossbar array, particularly in the memory cell and ADC, which can affect the accuracy of DNN inference [74,75]. Additionally, noise within analog computation can also harm DNN inference accuracy.…”

Section: Challenges With Imc Architecturesmentioning

confidence: 99%

“…In [76], VAT is combined with dynamic precision quantization to mitigate the post-mapping accuracy loss. Another approach proposed in [75] involves injecting RRAM macro measurement results that include variability and noise during the DNN training process to improve the DNN accuracy of the RRAM IMC hardware. Mohanty et al [88] proposes post-mapping training by selecting a random subset of weights and mapping them to an on-chip memory to recover the accuracy.…”

Section: Block Diagram Of a Sram-based Imc Crossbar Array An Array Of...mentioning

confidence: 99%

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End-to-End Benchmarking of Chiplet-Based In-Memory Computing

Krishnan,

K. Mandal,

A. Goksoy

et al. 2023

Neuromorphic Computing

Self Cite

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In-memory computing (IMC)-based hardware reduces latency and energy consumption for compute-intensive machine learning (ML) applications. Several SRAM/RRAM-based IMC hardware architectures to accelerate ML applications have been proposed in the literature. However, crossbar-based IMC hardware poses several design challenges. We first discuss the different ML algorithms recently adopted in the literature. We then discuss the hardware implications of ML algorithms. Next, we elucidate the need for IMC architecture and the different components within a conventional IMC architecture. After that, we introduce the need for 2.5D or chiplet-based architectures. We then discuss the different benchmarking simulators proposed for monolithic IMC architectures. Finally, we describe an end-to-end chiplet-based IMC benchmarking simulator, SIAM.

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Section: Challenges With Imc Architecturesmentioning

confidence: 99%

Section: Block Diagram Of a Sram-based Imc Crossbar Array An Array Of...mentioning

confidence: 99%

End-to-End Benchmarking of Chiplet-Based In-Memory Computing

Krishnan,

K. Mandal,

A. Goksoy

et al. 2023

Neuromorphic Computing

Self Cite

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“…While this work performs experiments using noise models obtained from various SRAM arrays, it still lacks a full-fledged hardware demonstration. Cherupally et al ( 2021 ) obtain a noise model of a RRAM-based crossbar often found in analog in-memory computing architectures. The noise model is then used in simulation to study the adversarial robustness of neural networks deployed on such a crossbar.…”

Section: Related Workmentioning

confidence: 99%

Adversarial attacks on spiking convolutional neural networks for event-based vision

Büchel

Lenz²,

Hu³

et al. 2022

Front. Neurosci.

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Event-based dynamic vision sensors provide very sparse output in the form of spikes, which makes them suitable for low-power applications. Convolutional spiking neural networks model such event-based data and develop their full energy-saving potential when deployed on asynchronous neuromorphic hardware. Event-based vision being a nascent field, the sensitivity of spiking neural networks to potentially malicious adversarial attacks has received little attention so far. We show how white-box adversarial attack algorithms can be adapted to the discrete and sparse nature of event-based visual data, and demonstrate smaller perturbation magnitudes at higher success rates than the current state-of-the-art algorithms. For the first time, we also verify the effectiveness of these perturbations directly on neuromorphic hardware. Finally, we discuss the properties of the resulting perturbations, the effect of adversarial training as a defense strategy, and future directions.

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“…Read et al [ 10 ] reverse engineered the weights and biases of DNN models mapped on analog CIM systems. Cherupally et al [ 11 ] studied adversarial attacks on analog RRAM‐based CIM systems. In this study, we analyze CIM privacy breach vulnerabilities by reconstructing users’ private input data from power side‐channel profiling of CIM systems.…”

Section: Introductionmentioning

confidence: 99%

PowerGAN: A Machine Learning Approach for Power Side‐Channel Attack on Compute‐in‐Memory Accelerators

Wang,

Wu,

Park

et al. 2023

Advanced Intelligent Systems

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Analog compute‐in‐memory (CIM) systems are promising candidates for deep neural network (DNN) inference acceleration. However, as the use of DNNs expands, protecting user input privacy has become increasingly important. Herein, a potential security vulnerability is identified wherein an adversary can reconstruct the user's private input data from a power side‐channel attack even without knowledge of the stored DNN model. An attack approach using a generative adversarial network is developed to achieve high‐quality data reconstruction from power leakage measurements. The analyses show that the attack methodology is effective in reconstructing user input data from power leakage of the analog CIM accelerator, even at large noise levels and after countermeasures. To demonstrate the efficacy of the proposed approach, an example of CIM inference of U‐Net for brain tumor detection is attacked, and the original magnetic resonance imaging medical images can be successfully reconstructed even at a noise level of 20% standard deviation of the maximum power signal value. This study highlights a potential security vulnerability in emerging analog CIM accelerators and raises awareness of needed safety features to protect user privacy in such systems.

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Improving the accuracy and robustness of RRAM-based in-memory computing against RRAM hardware noise and adversarial attacks

Cited by 6 publications

References 30 publications

End-to-End Benchmarking of Chiplet-Based In-Memory Computing

End-to-End Benchmarking of Chiplet-Based In-Memory Computing

Adversarial attacks on spiking convolutional neural networks for event-based vision

PowerGAN: A Machine Learning Approach for Power Side‐Channel Attack on Compute‐in‐Memory Accelerators

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