Improving testing and diagnosis efficiency for regular memory arrays

Abstract

Built-in self-test (BIST) is one of the most widely used design-for-testability (DFT) techniques, particularly for embedded random access memory (RAM). To ease the test and diagnosis flow, we have previously developed a synthesis compiler, called BRAINS which stands for BIST for RAM in Seconds. It possesses many nice features, such as accessibility, scalability, programmability, and flexibility, thereby improving the testability, yield, and reliability. However, for regular arrays, the conventional flow attaches a BIST circuit to each memory element, and scans in test patterns or performs sequential diagnosis, so is inefficient in terms of test time. In this work, we extend the BRAINS functions by taking advantage of the regular structure. With these extensions, the test and diagnosis flow becomes very simple. In the experiments on a 32-core array, the overall test time can be reduced by 6 to 23 times with only minor area overhead varying from 10% to 17%, as compared with the original BRAINS design.