Improving Pathfinder Algorithm Perfomance for FPGA Routing

Zapletina, Mariya A.; Zheleznikov, D.A.; Гаврилов, С. В.

doi:10.1109/elconrus51938.2021.9396608

Cited by 7 publications

(1 citation statement)

References 9 publications

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“…Currently, there is no new algorithm that can replace the dominant position of the PathFinder algorithm in the field of serial FPGA routing [6] . Existing routing methods mainly include improving the PathFinder algorithm [7] , simplifying FPGA structures, and setting macro modules. Encapsulating commonly used circuit modules into macro cells [8] can significantly reduce FPGA routing time.…”

Section: Introductionmentioning

confidence: 99%

An FPGA routing algorithm to improve efficiency and quality

Zhu,

2023

Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023)

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With the continuous increase in the size and integration of Field Programmable Gate Arrays (FPGAs), the running time of FPGA Electronic Design Automation (EDA) software has become longer and longer, gradually constraining the healthy development of FPGAs. Among the various stages of the FPGA EDA process, the routing stage is one of the most timeconsuming, and the routing results directly affect the performance of the implemented circuit. To address this issue, this paper proposes a high-efficiency and high-quality FPGA routing algorithm, EQRouter. EQRouter improves the performance of the routing algorithm by enhancing the maze routing algorithm and the rip-up and re-route strategy in the Versatile Place and Route (VPR) routing algorithm. Experimental results show that, compared to the VPR 7 router, EQRouter achieves a 24.6%, 14%, and 12% reduction in routing time, critical path delay, and circuit bus length, respectively, on 10 MCNC benchmark circuits.

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Section: Introductionmentioning

confidence: 99%