Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology

Oklobdzija, Vojin G.; Villeger, D.

doi:10.1109/92.386228

Cited by 106 publications

(45 citation statements)

References 9 publications

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“…1, there are at most 10 digits to be compressed in one column in the partial product array. According to [15], a (10:2) compressor will have less delay compared to combinations of multi-stage (3:2) compressor, but one stage of (10:2) compressor cannot take advantage of pipeline design. So we adopt a combination of (4:2) compressor and (3:2) compressor in the design of compressor array.…”

Section: Pipelined Multiplier Supporting Multi-operand Additionmentioning

confidence: 99%

Prototyping design of a flexible DSP block with pipeline structure for FPGA

Wang

Lai

2016

IEICE Electron. Express

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Embedded hard DSP block effectively improves FPGA performance for arithmetic circuits. This paper proposes a novel DSP architecture. By adopting a new Compressor Array, the proposed DSP can additionally supports multi-operand addition which current commercial devices do not support. This makes the DSP block more versatile to cover a wider range of applications. But supporting multi-operand addition will significantly increase routing congestion. To alleviate timing degeneration caused by the more congestion routing, we implement a pipelined design in the Compressor Array. The proposed DSP block is fabricated in 1P10M 65 nm bulk CMOS process, Test results show a 53.7% reduction in critical path delay compared to the Field Programmable Compressor Tree (FPCT).

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Section: Pipelined Multiplier Supporting Multi-operand Additionmentioning

confidence: 99%

Prototyping design of a flexible DSP block with pipeline structure for FPGA

Wang

Lai

2016

IEICE Electron. Express

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“…In other words, the arrival time of the bits at the final CPA is nonuniform, unlike the case of multiinput addition. Based on this observation, Oklobdzija and Villeger [1995] argued that the final CPA of a multiplier should be implemented as a hybrid adder, which uses a small and slow CPA, such as an RCA, for the low-order bits, and a faster adder, such as a carry-select adder for the higher-order bits.…”

Section: Adder and Compressor Treesmentioning

confidence: 99%

“…The key is not to use trees of traditional carry-propagate adders, that is, circuits that produce the sum of two (signed) binary integers; instead, the integers are aggregated together using a circuit called a compressor tree. Numerous methods for compressor tree generation have been published since their introduction in the early 1960s [Wallace 1964;Dadda 1965;Swartzlander 1973;Stenzel et al 1977;Weinberger 1981;Santoro and Horowitz 1988;Song and De Micheli 1991;Fadavi-Arkedani 1993;Oklobdzija and Villeger 1995;Stelling and Oklobdzija 1996;Stelling et al 1998;Kwon et al 2002;Um and Kim 2002;Mora Mora et al 2006;Verma and Ienne 2007a], mostly in the context of parallel multiplication; more generally, these circuits can also sum k > 2 integers.…”

Section: Introductionmentioning

confidence: 99%

“…This article, an extension of prior work by Parandeh-Afshar et al [2008a], introduces and evaluates a new logic cell, based on the Altera Adaptive Logic Module (ALM), that has an additional carry chain, which allows it to be configured as a 6:2 or 7:2 compressor; this compressor belongs to a well-known class of circuits that have been used for successful synthesis of ASIC multipliers in the past [Weinberger 1981;Song and De Micheli 1991;Oklobdzija and Villeger 1995]. By combining the strengths of the GPC mapping with the use of 6:2 or 7:2 compressors, when possible, faster compressor trees can be realized on the FPGA.…”

Section: Introductionmentioning

confidence: 99%

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An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor

Parandeh-Afshar

Brisk

Ienne

2009

ACM Trans. Reconfigurable Technol. Syst.

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To improve FPGA performance for arithmetic circuits that are dominated by multi-input addition operations, an FPGA logic block is proposed that can be configured as a 6:2 or 7:2 compressor. Compressors have been used successfully in the past to realize parallel multipliers in VLSI technology; however, the peculiar structure of FPGA logic blocks, coupled with the high cost of the routing network relative to ASIC technology, renders compressors ineffective when mapped onto the general logic of an FPGA. On the other hand, current FPGA logic cells have already been enhanced with carry chains to improve arithmetic functionality, for example, to realize fast ternary carry-propagate addition. The contribution of this article is a new FPGA logic cell that is specialized to help realize efficient compressor trees on FPGAs. The new FPGA logic cell has two variants that can respectively be configured as a 6:2 or a 7:2 compressor using additional carry chains that, coupled with lookup tables, provide the necessary functionality. Experiments show that the use of these modified logic cells significantly reduces the delay of compressor trees synthesized on FPGAs compared to state-of-the-art synthesis techniques, with a moderate increase in area and power consumption.

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“…In digital systems, adders effect overall system performance. Therefore to enhance its performance had become an important aim [1]- [3].…”

Section: Introductionmentioning

confidence: 99%

Efficient Design of 1- bit Low Power Full Adder using GDI Technique

2017

IJSR

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Abstract:The two important issues in designing of analog circuits are area and power which can be controlled by various parameters.Addition is one of the important mathematical operations which serve as a building block. A low power full adder is the important circuit in the designing of other large circuits. In this paper, three low power full adders are designed using basic gate OR, AND, XOR and XNOR. These gates are designed by using GDI technique. When the number of transistors are decreased then the power consumption and area is reduced.GDI is a new technique for low power digital circuits .This techniques reduce the power consumption, propagation delay and transistor count of digital circuits. The adder cell consists of XOR and XNOR gates. The performance of different adder is compared in respect of various parameters. From results, its cleared that the due to less transistor count the power consumption and area is reduced DSCH and MICROWIND tool is used for the circuit design and simulation of it.

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Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology

Cited by 106 publications

References 9 publications

Prototyping design of a flexible DSP block with pipeline structure for FPGA

Prototyping design of a flexible DSP block with pipeline structure for FPGA

An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor

Efficient Design of 1- bit Low Power Full Adder using GDI Technique

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