Improving Low Power Processor Efficiency with Static Pipelining

Abstract

A new generation of mobile applications requires reduced energy consumption without sacrificin execution performance. In this paper, we propose to respond to these conflictin demands with an innovative statically pipelined processor supported by an optimizing compiler. The central idea of the approach is that the control during each cycle for each portion of the processor is explicitly represented in each instruction. Thus the pipelining is in effect statically determined by the compiler. The benefit of this approach include simpler hardware and that it allows the compiler to perform optimizations that are not possible on traditional architectures. The initial results indicate that static pipelining can significantl reduce power consumption without adversely affecting performance.

Software-controlled processor stalls for time and energy efficient data locality optimization

“…In other situations, transforming the code to execute within a power budget and save energy, may harm performance. Significant efforts have been made to achieve a better balance between the two [15], [11], [7], [14], [8], [6], [5], [9]. Dynamic Voltage and Frequency Scaling (DVFS) is a common technique for saving energy, by scaling down voltage and frequency.…”

“…Apart from DVFS techniques, other proposals target compiler-architecture collaborations, which enable a wiser use of the micro-architecture based on static information [6], [5], [16]. In particular, Finlayson et al [6], [5] focus on improving the processor pipeline and propose an entirely statically pipelined processor, relying on an optimizing compiler to insert control information for each instruction.…”

“…In particular, Finlayson et al [6], [5] focus on improving the processor pipeline and propose an entirely statically pipelined processor, relying on an optimizing compiler to insert control information for each instruction. Thus, redundant operations performed by traditional processor pipelines are eliminated (e.g., unnecessary register reads and writes, when their consumers retrieve such information from forwarding).…”

An Overview of Static Pipelining

“…The code above was compiled with the VPO [3] MIPS port, with full optimizations applied, and the main loop is shown in Figure 3(b). In this example, r [9] is used as a pointer to the current array element, r [5] is a pointer to the end of the array, and r [6] holds the value m. The requirements for each iteration of the loop are shown in Figure 3(c).…”

“…In this paper, we present an overview of a technique called static pipelining [6] which aims to provide the performance benefits of pipelining in a more energy-efficient manner. With static pipelining, the control for each portion of the processor is explicitly represented in each instruction.…”