Improving gateway performance with a routing-table cache

Feldmeier, David C.

doi:10.1109/infcom.1988.12930

Cited by 61 publications

(48 citation statements)

References 2 publications

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“…Schemes in [7,24,28] typically use 2Mbits on-chip Bloom filters. An IP cache of the same size can provide a fast onchip IP lookup solution since the IP cache miss ratio is small [9,25]. Note that if there is a cache miss in an IP lookup, we need to complete the IP lookup by using contemporary off-chip hashbased IP lookup schemes.…”

Section: Background and Related Work 21 Ip Lookup Schemesmentioning

confidence: 99%

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A new IP lookup cache for high performance IP routers

Liao

Bhuyan

2010

Proceedings of the 47th Design Automation Conference

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IP lookup is in the critical data path in a high speed router. In this paper, we propose a new on-chip IP cache architecture for a high performance IP lookup. We design the IP cache along two important axes: cache indexing and cache replacement policies. First, we study various hash performance and employ 2-Universal hashing for our IP cache. Second, coupled with our cache indexing scheme, we present a progressive cache replacement policy by considering Internet traffic characteristics. Our experiments with IP traces show that our IP cache reduces the miss ratio by 15% and a small 32KB IP cache can achieve as high as 2Tbps routing throughput.

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Section: Background and Related Work 21 Ip Lookup Schemesmentioning

confidence: 99%

“…Authors in [3,9,25] present an IP lookup cache architecture since IP traces exhibit strong duplication of destination addresses in the form of temporal locality. By envisioning the benefits of an IP cache, authors in [2,12] place the IP cache in front of TCAM-or triebased IP lookup tables to have multifold increase in throughput.…”

Section: Introductionmentioning

confidence: 99%

A new IP lookup cache for high performance IP routers

Liao

Bhuyan

2010

Proceedings of the 47th Design Automation Conference

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“…Finding a particular destination in this database of IP destination-to-next-hop association is easier because an exact match is done instead of the more expensive best-match operation of the routing table. So, most routers relied on route caches [20,21]. The route caching techniques rely on there being enough locality in the trac so that the cache hit rate is suciently high and the cost of a routing lookup is amortized over several packets.…”

Section: Route Lookupmentioning

confidence: 99%

“…The justi®cation for route caching is that packet arrivals are temporally correlated, so that if a packet belonging to a new ow arrives then more packets belonging to the same¯ow can be expected to arrive in the near future. Route caching of IP destination/next-hop address pairs will decrease the average processing time per packet if locality exists for packet addresses [20,21]. Still, the performance of the traditional bus-based router depends heavily on the throughput of the shared bus and on the forwarding speed of the central processor.…”

Section: Bus-based Router Architectures With Single Processormentioning

confidence: 99%

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On the design of IP routers Part 1: Router architectures

Aweya

2000

Journal of Systems Architecture

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Internet Protocol (IP) networks are currently undergoing transitions that mandate greater bandwidths and the need to prepare the network infrastructures for converged trac (voice, video, and data). Thus, in the emerging environment of high performance IP networks, it is expected that local and campus area backbones, enterprise networks, and Internet Service Providers (ISPs) will use multigigabit and terabit networking technologies where IP routers will be used not only to interconnect backbone segments but also to act as points of attachments to high performance wide area links. Special attention must be given to new powerful architectures for routers in order to play that demanding role. In this paper, we describe the evolution of IP router architectures and highlight some of the performance issues aecting IP routers. We identify important trends in router design and outline some design issues facing the next generation of routers. It is also observed that the achievement of high throughput IP routers is possible if the critical tasks are identi®ed and special purpose modules are properly tailored to perform them. Ó

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IP router architectures: an overview

Aweya

2001

Int J Communication

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SUMMARYIn the emerging environment of high performance IP networks, it is expected that local and campus area backbones, enterprise networks, and internet service providers (ISPs) will use multigigabit and terabit networking technologies where IP routers will be used not only to interconnect backbone segments but also to act as points of attachments to high performance wide area links. Special attention must be given to new powerful architectures for routers in order to play that demanding role. In this paper, we identify important trends in router design and outline some design issues facing the next generation of routers. It is also observed that the achievement of high throughput IP routers is possible if the critical tasks are identi"ed and special purpose modules are properly tailored to perform them.

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Improving gateway performance with a routing-table cache

Cited by 61 publications

References 2 publications

A new IP lookup cache for high performance IP routers

A new IP lookup cache for high performance IP routers

On the design of IP routers Part 1: Router architectures

IP router architectures: an overview

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