Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications

Gracia-Morán, Joaquín; Saiz-Adalid, Luis-J.; Gil-Tomás, Daniel; Gil-Vicente, Pedro-J.

doi:10.1109/tvlsi.2018.2837220

Cited by 48 publications

(28 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Because of embedded combined CAC-ECC in the NI, the router of NoC presented huge power consumption; hence, there is a need of reducing the power consumption in NoC. By analyzing various error control schemes in NI, flexible unequal error control (FUEC) methodology is introduced and generalized to any kind of error control codes [10].…”

Section: Advanced Noc Routermentioning

confidence: 99%

Combined Crosstalk Avoidance Code with Error Control Code for Detection and Correction of Random and Burst Errors

Kummary¹,

Dananjayan²,

Viswanath³

et al. 2020

Coding Theory

View full text Add to dashboard Cite

Error correction codes are majorly important to detect and correct occurred errors because of various noise sources. When the technology is scaling down, the effect of noise sources is high. The coupling capacitance is one of the main constraints to affect the performance of on-chip interconnects. Because of coupling capacitance, the crosstalk is introduced at on-chip interconnecting wires. To control the single or multiple errors, an efficient error correction code is required. By combining crosstalk avoidance with error control code, the reliable intercommunication is obtained in network-on-chip (NoC)-based system on chip (SoC). To reduce the power consumption of error control codes, the bus invert-based low-power code is integrated to network interface of NoC. The advanced work is designed and implemented with Xilinx 14.7; thereby the performance of improved NoC is evaluated and compared with existing work. The 8 × 8 mesh-based NoC is simulated at various traffic patterns to analyze the energy dissipation and average data packet latency.

show abstract

Section: Advanced Noc Routermentioning

confidence: 99%

Combined Crosstalk Avoidance Code with Error Control Code for Detection and Correction of Random and Burst Errors

Kummary¹,

Dananjayan²,

Viswanath³

et al. 2020

Coding Theory

View full text Add to dashboard Cite

show abstract

“…For thid, we employed a searching methodology based on the errors to be corrected and/or detected [19]. Although this methodology was initially employed to design flexible unequal error control (FUEC) codes, it has been successfully used to design different families of codes (e.g., [18,20,21]). First, let us briefly describe this methodology.…”

Section: Low Redundancy and Reduced Overhead (Lrro) Double Error Correction Codesmentioning

confidence: 99%

“…All LRRO DEC codes presented in this paper, as well as the considered BCH DEC codes, have been implemented and simulated to check if they achieve the expected error coverage. We implemented a simulation-based error injection tool [21] with which we could analyze the error coverage of the different ECCs. This tool can inject diverse error models.…”

Section: Implementation and Logic Synthesismentioning

confidence: 99%

Reducing the Overhead of BCH Codes: New Double Error Correction Codes

et al. 2020

Self Cite

View full text Add to dashboard Cite

The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word lengths, which do not frequently match those employed in digital systems. This paper focuses on double error correction (DEC) codes for word lengths that are in powers of two (8, 16, 32, and 64), which are commonly used in memories. We also focus on hardware implementations of the encoder and decoder circuits for very fast operations. This work proposes new low redundancy and reduced overhead (LRRO) DEC codes, with the same redundancy as the equivalent BCH DEC codes, but whose encoder, and decoder circuits present a lower overhead (in terms of propagation delay, silicon area usage and power consumption). We used a methodology to search parity check matrices, based on error patterns, in order to design the new codes. We implemented and synthesized them, and compared their results with those obtained for the BCH codes. Our implementation of the decoder circuits achieved reductions between 2.8% and 8.7% in the propagation delay, between 1.3% and 3.0% in the silicon area, and between 15.7% and 26.9% in the power consumption. Therefore, we propose LRRO codes as an alternative for protecting information against multiple errors.

show abstract

“…However, ECCs have power, delay, and area overhead. 7,8 Hence, researchers are focusing on designing radiation-hardened cells to mitigate soft-error. 7 Conventional 6T SRAM does not possesses radiation-hardened characteristics, because an SEU occurring at one storage node propagates to the other storage node due to the positive feedback of its cross-coupled inverters.…”

mentioning

confidence: 99%

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Pal

Divya

et al. 2021

Circuit Theory & Apps

View full text Add to dashboard Cite

In advanced technology, static random-access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high-energy particle strikes, which cause soft-error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation-hardened readdecoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read-decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02Â/1.06Â/1.07Â/1.08Â over NS10T/RHD12T/PS10T/RHBD10T at V DD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single-event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. K E Y W O R D Sdigital circuit, low power design, memory design, read stability, SRAM | INTRODUCTIONSatellites have become an integral part of human society, as we rely on satellite communication for a wide range of services, from meteorology to disaster monitoring, from navigation systems to military operations, and so on. 1 As the technology is advancing, lightweight satellites are replacing heavyweight satellites because of their higher manufacturing cost. 2 Since lightweight satellites have limited resources, they require high-density memory cells, and static random-access memory (SRAM) cells are the best alternative for space applications because of their high packing density and improved logic performance. 1 Space presents extreme conditions, like temperature fluctuations and radiation. Due to the weak geomagnetic field in space, radiation and energized particles increase. To withstand this harsh environment, special electronic components and circuits are used. Once a radiation particle strikes a logic circuit at its sensitive node, it generates electron-hole pairs (Figure 1A). These pairs become separated and accumulate at the sensitive node. 3 The accumulated charge at the sensitive node then generates a transient voltage pulse. If enough charge (i.e., critical charge, Q C ) is

show abstract

Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications

Cited by 48 publications

References 29 publications

Combined Crosstalk Avoidance Code with Error Control Code for Detection and Correction of Random and Burst Errors

Combined Crosstalk Avoidance Code with Error Control Code for Detection and Correction of Random and Burst Errors

Reducing the Overhead of BCH Codes: New Double Error Correction Codes

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Contact Info

Product

Resources

About