Improving Energy Efficiency through Parallelization and Vectorization on Intel Core i5 and i7 Processors

Cebrian, Juan M.; Natvig, Lasse; Meyer, Jan Christian

doi:10.1109/sc.companion.2012.93

Cited by 13 publications

(11 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The energy and power efficiency is subject to different research fields. Especially, in the field of multi-threaded, parallel and distributed computing [3], [8], [9]. In our work we isolate the effects of vectorization on energy efficiency 8…”

Section: Related Workmentioning

confidence: 99%

On the energy consumption of Load/Store AVX instructions

Jakobs

Rünger

2018

Proceedings of the 2018 Federated Conference on Computer Science and Information Systems

View full text Add to dashboard Cite

The energy efficiency of program executions is an active research field in recent years and the influence of different programming styles on the energy consumption is part of the research effort. In this article, we concentrate on SIMD programming and study the effect of vectorization on performance as well as on power and energy consumption. Especially, SIMD programs using AVX instructions are considered and the focus is on the AVX load and store instruction set. Several semantically similar but different load and store instructions are selected and are used to build different program versions of for the same algorithm. As example application, the Gaussian elimination has been chosen due to its interesting feature of using arrays of varying length in each factorization step. Five different SIMD program versions of the Gaussian elimination have been implemented, each of which uses different load and store instructions. Performance, power, and energy measurements for all program versions are provided for the Intel Sandy Bridge, Haswell and Skylake architectures and the results are discussed and analyzed.

show abstract

Section: Related Workmentioning

confidence: 99%

On the energy consumption of Load/Store AVX instructions

Jakobs

Rünger

2018

Proceedings of the 2018 Federated Conference on Computer Science and Information Systems

View full text Add to dashboard Cite

show abstract

“…There are many works in the literature that focus on improving performance under a given (constant) power budget [12,17,18], including several that specifically use TDP as the power constraint [13,15]. There is also work on energy efficiency [4] and on reliability [11] under TDP constraints, and on power budgeting based on reinforcement learning [6].…”

Section: Related Workmentioning

confidence: 99%

“…In [4], the authors evaluate the energy efficiency of different processors from Intel's i5 and i7 family, using selected benchmarks with variable core counts and vectorization techniques, while using TDP as the power constraint.…”

Section: Related Workmentioning

confidence: 99%

TSP: thermal safe power

Pagani

Khdr

Munawar

et al. 2014

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis

View full text Add to dashboard Cite

Chip manufacturers provide the Thermal Design Power (TDP) for a specific chip. The cooling solution is designed to dissipate this power level. But because TDP is not necessarily the maximum power that can be applied, chips are operated with Dynamic Thermal Management (DTM) techniques. To avoid excessive triggers of DTM, usually, system designers also use TDP as power constraint. However, using a single and constant value as power constraint, e.g., TDP, can result in big performance losses in many-core systems. Having better power budgeting techniques is a major step towards dealing with the dark silicon problem.This paper presents a new power budget concept, called Thermal Safe Power (TSP), which is an abstraction that provides safe power constraint values as a function of the number of simultaneously operating cores. Executing cores at any power consumption below TSP ensures that DTM is not triggered. TSP can be computed offline for the worst cases, or online for a particular mapping of cores. Our simulations show that using TSP as power constraint results in 50.5% and 14.2% higher average performance, compared to using constant power budgets (both per-chip and per-core) and a boosting technique, respectively. Moreover, TSP results in dark silicon estimations which are more optimistic than estimations using constant power budgets.

show abstract

“…It can be also used to speed up stochastic methods such as Monte Carlo simulations, image processing tasks, etc. The use of AVX can also improve the power costs and energy efficiency of various computations . It represents a CPU‐based alternative to GPU parallelization that is implemented in modern CPUs and is, in many cases, able to outperform GPU‐based solutions …”

Section: Introductionmentioning

confidence: 99%

“…The use of AVX can also improve the power costs and energy efficiency of various computations. 14,15 It represents a CPU-based alternative to GPU parallelization that is implemented in modern CPUs and is, in many cases, able to outperform GPU-based solutions. 13 In this work, the acceleration of an advanced image steganographic algorithm by the use of AVX instructions is proposed, implemented, and experimentally evaluated.…”

mentioning

confidence: 99%

JPEG steganography with particle swarm optimization accelerated by AVX

Snášel

Krömer

Šafařík

et al. 2019

Concurrency and Computation

View full text Add to dashboard Cite

Summary Digital steganography aims at hiding secret messages in digital data transmitted over insecure channels. The JPEG format is prevalent in digital communication, and images are often used as cover objects in digital steganography. Optimization methods can improve the properties of images with embedded secret but introduce additional computational complexity to their processing. AVX instructions available in modern CPUs are, in this work, used to accelerate data parallel operations that are part of image steganography with advanced optimizations.

show abstract

Improving Energy Efficiency through Parallelization and Vectorization on Intel Core i5 and i7 Processors

Cited by 13 publications

References 18 publications

On the energy consumption of Load/Store AVX instructions

On the energy consumption of Load/Store AVX instructions

TSP: thermal safe power

JPEG steganography with particle swarm optimization accelerated by AVX

Contact Info

Product

Resources

About