Improving EHW performance introducing a new decomposition strategy

Abstract

Abstract-This paper describes a new type of decomposition strategy for Evolvable Hardware, which tackles the problem of scalability. Several logic circuits from the MCNC benchmark have been evolved and compared with other Evolvable Hardware techniques. The results demonstrate that the proposed method improves the evolution of logic circuits in terms of time and fitness function in comparison with BIE and standard EHW.

Task decomposition and evolvability in intrinsic evolvable hardware

“…However, high input count is a problem in the case of intrinsic evolution as well, since the number of IOs is limited. Therefore, a possible direction for future work could be to employ a MUX array to compress a large number of inputs-in a similar fashion as it is done in [10]-before applying them to the evolvable sub-system. A further improvement in the case of the parallelised architecture could be to use multichromosome genomes, where each chromosome represents only parts of the hardware configuration that are responsible for the same output, similar to [17].…”

“…Each chromosome thereby represents an independent cartesian genetic program (CGP), which is required to solve the task for only one of the outputs. Approaches where complex tasks are automatically partitioned by evolving modules, which satisfy subsets of the demanded functionality can be found in [3], [4], [10], [12]. In the case of [4] the obtained modules are merged and optimised in terms of redundancy in a second stage (incremental evolution) of the evolutionary algorithm (EA).…”

On Evolution of Relatively Large Combinational Logic Circuits

“…• the number of generations required to completely evolve logic circuits is mainly dependant on the number of inputs instead of the number of outputs, which is shown in [3].…”

“…By using this decomposition strategy the number of generations required to evolve the circuits is much smaller; furthermore this method allows the evolution of larger circuits [3]. This sub-system G, which has fewer inputs and more outputs than the original ones, can be evolved using either the traditional EHW approach or any other scalable approach such as divide-and-conquer, bidirectional incremental evolution, etc.…”

“…Therefore, it is not applicable for the evolution of FPGA-based logic circuits. Based on decomposition strategies, several approaches to overcoming scalability problem have been introduced such as: divide-andconquer [15]; bi-directional incremental evolution (SO-BIE) [2] and the generalised disjunction decomposition, a new decomposition strategy for evolvable hardware introduced by the author in [3]. Regarding the divide and conquer method, so called increased incremental evolution [16] has been introduced to reduce the search space.…”