Improving cache performance by combining cost-sensitivity and locality principles in cache replacement algorithms

Sheikh, Rami; Kharbutli, Mazen

doi:10.1109/iccd.2010.5647594

Cited by 18 publications

(10 citation statements)

References 16 publications

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“…It is clear that the characteristics of this benchmark affect the correlation between miss rate improvement and IPC improvement. Many prior studies have shown that the correlation between the miss rate and cache performance is not straightforward for modern systems since cache misses have different costs [18,20,21]. The cost may be of latency, power consumption, bandwidth consumption, etc.…”

Section: Impact Of Cache Associativity On Miss Ratementioning

confidence: 97%

“…In the context of uniprocessors, Jeong et al [18,19] proposed a cost-sensitive cache replacement algorithm that assigns cost based on whether a block's next access is predicted to be a load (high-cost) or store (low-cost). Cost-sensitive replacement algorithms to reduce the cost of cache misses rather than miss rates have been proposed [10][11][12][13][14][15][16][17][18][19][20][21][22].…”

Section: Related Workmentioning

confidence: 99%

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A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines

Thuan

Choi

Kim

et al. 2015

Microprocessors and Microsystems

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Section: Impact Of Cache Associativity On Miss Ratementioning

confidence: 97%

Section: Related Workmentioning

confidence: 99%

A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines

Thuan

Choi

Kim

et al. 2015

Microprocessors and Microsystems

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“…Authors in [14] presented Locality-Aware Cost-Sensitive (LACS) cache replacement strategy that brings together cost sensitivity and locality principles. The cost of a cache block is estimated by LACS from number of instructions issued by processor during cache-miss on the block and then the blocks with poor locality and less cost are victimized for maximizing overall cache performance.…”

Section: Literature Surveymentioning

confidence: 99%

A Computationally Efficient P-LRU based Optimal Cache Heap Object Replacement Policy

Khan¹,

Olanrewaju²,

Mir³

et al. 2017

ijacsa

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Abstract-The recent advancement in the field of distributed computing depicts a need of developing highly associative and less expensive cache memories for the state-of-art processors i.e., Intel Core i6, i7, etc. Hence, various conventional studies introduced cache replacement policies which are one of the prominent key factors to determine the effectiveness of a cache memory. Most of the conventional cache replacement algorithms are found to be as not so efficient on memory management and complexity analysis. Therefore, a significant and thorough analysis is required to suggest a new optimal solution for optimizing the state-of-the-art cache replacement issues. The proposed study aims to conceptualize a theoretical model for optimal cache heap object replacement. The proposed model incorporates Tree based and MRU (Most Recently Used) pseudo-LRU (Least Recently Used) mechanism and configures it with JVM's garbage collector to replace the old referenced objects from the heap cache lines. The performance analysis of the proposed system illustrates that it outperforms the conventional state of art replacement policies with much lower cost and complexity. It also depicts that the percentage of hits on cache heap is relatively higher than the conventional technologies.

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“…The study of authors in [8] incorporated a combined cost sensitivity and locality principle to improve the cache performance associated with the cache replacement algorithms. They have defined a new memory hierarchy which is capable of reducing the average memory access time.…”

Section: Literature Surveymentioning

confidence: 99%

An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches

Olanrewaju

Baba

Khan

et al. 2016

2016 Fourth International Conference on Parallel, Distributed and Grid Computing (PDGC)

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Abstract-In the recent times, various challenges are being encountered during SRAM cache design and development which lead to a situation of converting the memory cell technologies into on-chip embedded caches. The current research statistics towards cache designing reveals that Spin Torque Transfer Magnetic RAMs, preferably termed as STT-MRAMs has become one of the most promising areas in the field of memory chip design. Hence, it gained a lot of attention from the researchers due to its dynamic direct map and data access policies for reducing the average cost i.e. time and energy optimization. Instead of having efficient main memory access capability, STTMRAMs suffer due to high error rate caused during stochastic switching in write operations. Cache replacement algorithms play a significant role in minimizing the error rate in write operations. The proposed study aims to offer a theoretical and analytical modeling of an efficient cache replacement scheme to overcome the error as mentioned above in L2-STT-MRAM caches. The performance analysis of the proposed algorithm ensures its effectiveness in reducing the error rate and cost overheads as compared to the conventional LRU technique implemented on SRAM cells.

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Improving cache performance by combining cost-sensitivity and locality principles in cache replacement algorithms

Cited by 18 publications

References 16 publications

A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines

A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines

A Computationally Efficient P-LRU based Optimal Cache Heap Object Replacement Policy

An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches

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