Improving bus test via I/sub DDT/ and boundary scan

Yang, Shih-Yu; Papachristou, C.A.; Taib-Azar, M.

doi:10.1109/dac.2001.935525

Cited by 1 publication

(2 citation statements)

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“…In [20], the authors present a method to detect defects in SoC interconnections using I DDT test (analyzing the variation of the dynamic current), boundary scan and tests of delay. A built-in self-test (BIST) methodology for testing the inter router links of a No-Chas been proposed in [21] considering the Maximum Aggressor Fault (MAF) model.…”

Section: Fault and Test Modelsmentioning

confidence: 99%

“…All routers are capable of using the lightweight adaptive routing (LAR) and data splitting (DS), however only the ones with faulty interconnections uses one of these techniques in order to minimize the overheads according to the fault case. By using test and diagnosis [10,[19][20][21], each router is configured with the information relative to the faulty interconnections (registers in each channel receive the information about faulty interconnections and multiplexers from DS technique receive the information about the specific faulty wires). In presence of defects, LAR technique is always the first choice, because it has minimal impact in communication time and power.…”

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confidence: 99%

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Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections

Kologeski

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Kastensmidt

et al. 2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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The use of fault-tolerant mechanism is essential to ensure the correct functionality of integrated circuits after manufacturing due to the massive number of faults that may occur during the process. In this work, we propose a set of fault-tolerant techniques to cope with faulty wires in Network-on-Chip (NoC). The most appropriate technique is chosen by taking into account the number of faulty wires and their location in the NoC. The goal is to combine different techniques to reduce overheads in area, delay and power. The use of testing and diagnosis can minimize costs associated with embedded faulttolerant mechanisms once the architecture adapts itself to work in different faulty scenarios. The proposed fault-tolerant strategy uses a lightweight adaptive routing combined with data splitting, which is able to send the data in one clock cycle. The power penalty has a low correlation with the number of faulty interconnections. Results for MPEG4 and VOPD applications running on the NoC with different faulty case-study scenarios show that the proposed techniques can tolerate many faulty interconnections with a low area, performance and power overheads.

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Section: Fault and Test Modelsmentioning

confidence: 99%

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confidence: 99%